相關申請的交叉參考

2016年(nian)3月(yue)22日(ri)提交(jiao)的(de)日(ri)本專利(li)申請(qing)第(di)號的(de)包括說明書、附圖和摘要的(de)公開結合(he)于此作為公開以(yi)引(yin)用(yong)的(de)方式全文引(yin)入(ru)本申請(qing)。

本(ben)發明涉及一種半導體器(qi)(qi)件，并(bing)且(qie)可應用于例如(ru)包括電(dian)(dian)平位移電(dian)(dian)路(lu)的半導體器(qi)(qi)件。

背景技術：

電(dian)(dian)(dian)(dian)(dian)平(ping)位移電(dian)(dian)(dian)(dian)(dian)路將(jiang)利用不(bu)同電(dian)(dian)(dian)(dian)(dian)源(yuan)(yuan)電(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)操(cao)作的(de)(de)每個(ge)電(dian)(dian)(dian)(dian)(dian)路中的(de)(de)信號幅度(du)轉換(huan)為(wei)對應于每個(ge)電(dian)(dian)(dian)(dian)(dian)源(yuan)(yuan)電(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)的(de)(de)幅度(du)。例如，在小型(xing)化半(ban)(ban)導體集成(cheng)電(dian)(dian)(dian)(dian)(dian)路中，從降(jiang)低電(dian)(dian)(dian)(dian)(dian)路的(de)(de)功耗和(he)元件的(de)(de)可靠性的(de)(de)觀點(dian)來看，采(cai)用低壓(ya)(ya)(ya)系(xi)統(tong)(tong)的(de)(de)電(dian)(dian)(dian)(dian)(dian)源(yuan)(yuan)電(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)。另一方面(mian)，在向/從外(wai)部電(dian)(dian)(dian)(dian)(dian)路輸(shu)出(chu)(chu)/輸(shu)入(ru)信號的(de)(de)輸(shu)入(ru)/輸(shu)出(chu)(chu)電(dian)(dian)(dian)(dian)(dian)路中，采(cai)用傳統(tong)(tong)的(de)(de)電(dian)(dian)(dian)(dian)(dian)源(yuan)(yuan)電(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)(高(gao)壓(ya)(ya)(ya)系(xi)統(tong)(tong)的(de)(de)電(dian)(dian)(dian)(dian)(dian)源(yuan)(yuan)電(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya))。因此，電(dian)(dian)(dian)(dian)(dian)平(ping)位移電(dian)(dian)(dian)(dian)(dian)路需(xu)要(yao)將(jiang)集成(cheng)電(dian)(dian)(dian)(dian)(dian)路內的(de)(de)低壓(ya)(ya)(ya)系(xi)統(tong)(tong)的(de)(de)電(dian)(dian)(dian)(dian)(dian)源(yuan)(yuan)電(dian)(dian)(dian)(dian)(dian)路中的(de)(de)信號電(dian)(dian)(dian)(dian)(dian)平(ping)轉換(huan)為(wei)高(gao)壓(ya)(ya)(ya)系(xi)統(tong)(tong)的(de)(de)電(dian)(dian)(dian)(dian)(dian)源(yuan)(yuan)電(dian)(dian)(dian)(dian)(dian)路中的(de)(de)信號電(dian)(dian)(dian)(dian)(dian)平(ping)。日本(ben)未審查專利申請公開第hei8(1996)-148988號(專利文獻1)公開了(le)一種技(ji)術，其(qi)中，基本(ben)上，負載元件、一個(ge)導電(dian)(dian)(dian)(dian)(dian)類(lei)型(xing)的(de)(de)mos晶(jing)體管(其(qi)柵(zha)(zha)(zha)極偏置(zhi)約為(wei)高(gao)壓(ya)(ya)(ya)的(de)(de)一半(ban)(ban))、相反導電(dian)(dian)(dian)(dian)(dian)類(lei)型(xing)的(de)(de)mos晶(jing)體管(約為(wei)高(gao)壓(ya)(ya)(ya)的(de)(de)一半(ban)(ban)的(de)(de)類(lei)似柵(zha)(zha)(zha)極偏置(zhi))和(he)相反導電(dian)(dian)(dian)(dian)(dian)類(lei)型(xing)的(de)(de)mos晶(jing)體管(其(qi)柵(zha)(zha)(zha)極提(ti)供有低幅度(du)的(de)(de)邏輯輸(shu)入(ru))以這(zhe)種順序串聯耦合在高(gao)壓(ya)(ya)(ya)和(he)gnd之間(jian)，并且施加給(gei)每個(ge)mos晶(jing)體管的(de)(de)柵(zha)(zha)(zha)極層的(de)(de)電(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)均(jun)減小。

技術實現要素：

當如日本未審查專利申請公開(kai)第hei8(1996)-148988號(hao)(hao)不采用具有高(gao)耐受電(dian)壓(ya)結(jie)(jie)構(gou)的晶體(ti)管(采用具有低(di)耐受電(dian)壓(ya)結(jie)(jie)構(gou)的晶體(ti)管)輸出高(gao)幅度信號(hao)(hao)(高(gao)電(dian)壓(ya)(vpp))時，超過低(di)幅度的信號(hao)(hao)(低(di)電(dian)壓(ya)(vdd))的漏極-源極電(dian)壓(ya)(vds)可以被施加(jia)至晶體(ti)管。

本發明的(de)(de)其他(ta)問(wen)題和新(xin)特征將從本說明書的(de)(de)描述和附圖中變得清(qing)楚(chu)。

以下簡(jian)要地說明本公開的(de)典型實(shi)施例(li)的(de)概(gai)況。

即，一(yi)種半導體(ti)器(qi)件包括電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)移電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)，其根據低幅度邏輯信(xin)號(hao)的(de)(de)輸入(ru)輸出高幅度信(xin)號(hao)。電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)移電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)包括串(chuan)聯(lian)耦合電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)、耦合至(zhi)第(di)(di)一(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)源(yuan)的(de)(de)第(di)(di)一(yi)柵極控制電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)、耦合至(zhi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)高于(yu)第(di)(di)一(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)源(yuan)的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)的(de)(de)第(di)(di)二(er)(er)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)源(yuan)的(de)(de)第(di)(di)二(er)(er)柵極控制電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)、以及布置(zhi)在第(di)(di)一(yi)柵極控制電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)與串(chuan)聯(lian)耦合電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)之間(jian)的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)轉(zhuan)換(huan)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)。電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)轉(zhuan)換(huan)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)向串(chuan)聯(lian)耦合電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)的(de)(de)n溝道mos晶體(ti)管的(de)(de)柵極提(ti)供第(di)(di)一(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)，該第(di)(di)一(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)低于(yu)第(di)(di)一(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)源(yuan)的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)且高于(yu)參考電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)源(yuan)的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)。

根據上述半導(dao)體(ti)(ti)器件(jian)，可以降(jiang)低(di)晶(jing)體(ti)(ti)管(guan)的漏極-源(yuan)極電壓。

附圖說明

圖1是示出根據比較示例的電(dian)平位移電(dian)路的電(dian)路圖；

圖(tu)2是示出(chu)柵(zha)極控制(zhi)電路(lu)的電路(lu)圖(tu)；

圖(tu)3是示出中(zhong)間電(dian)位(wei)生成電(dian)路的電(dian)路圖(tu)；

圖4是示出根據實施(shi)例1的電平位移(yi)電路的電路圖；

圖5是(shi)示出根據實施例1的半導體(ti)器件的塊狀圖；

圖(tu)6是(shi)示(shi)出(chu)根(gen)據實施例(li)2的電(dian)平位移電(dian)路(lu)的電(dian)路(lu)圖(tu)；

圖7是示出根據實施(shi)例2的信息設備的框(kuang)圖；

圖8是示(shi)出根據實(shi)施例3的電(dian)平位移電(dian)路(lu)的電(dian)路(lu)圖；

圖9是示出根據實施例(li)4的電(dian)平位移電(dian)路的電(dian)路圖；以及

圖(tu)10是示出根據實(shi)施(shi)例(li)5的電平位移(yi)電路的電路圖(tu)。

具體實施方式

以(yi)下，參照(zhao)附(fu)圖(tu)解釋比較示例和實施例。在以(yi)下說(shuo)明中，相同的符(fu)號(hao)或參考標號(hao)附(fu)接至相同的元(yuan)件，并且可以(yi)省略其(qi)重(zhong)復說(shuo)明。

本發(fa)(fa)明的(de)發(fa)(fa)明人研(yan)究(jiu)了根據(ju)(ju)低幅(fu)度(du)的(de)邏輯信號的(de)輸入(0v-vdd)來輸出高(gao)(gao)幅(fu)度(du)的(de)信號(0v-vpp)的(de)技術(以下稱為比較示(shi)(shi)例(li))，而(er)不采(cai)用高(gao)(gao)耐受電(dian)壓結構的(de)晶(jing)(jing)體(ti)(ti)管(guan)(guan)并(bing)且防(fang)止過量的(de)電(dian)壓被施(shi)加(jia)給晶(jing)(jing)體(ti)(ti)管(guan)(guan)的(de)柵極氧化(hua)物層(ceng)。圖(tu)1是示(shi)(shi)出根據(ju)(ju)比較示(shi)(shi)例(li)的(de)電(dian)平位移電(dian)路的(de)電(dian)路圖(tu)。

根據比較示例的(de)(de)電(dian)平位(wei)移(yi)電(dian)路(lu)lsr包括反(fan)(fan)相(xiang)(xiang)器(qi)(qi)inv和(he)(he)(he)(he)inv2、柵(zha)(zha)極(ji)控(kong)制電(dian)路(lu)gc、中間電(dian)位(wei)生成電(dian)路(lu)ivg和(he)(he)(he)(he)串(chuan)聯(lian)(lian)電(dian)路(lu)sc。用(yong)作柵(zha)(zha)極(ji)控(kong)制電(dian)路(lu)的(de)(de)反(fan)(fan)相(xiang)(xiang)器(qi)(qi)inv由p溝道mos晶(jing)(jing)體(ti)(ti)管(以(yi)下(xia)稱為“pmos晶(jing)(jing)體(ti)(ti)管”)qp1和(he)(he)(he)(he)n溝道mos晶(jing)(jing)體(ti)(ti)管(以(yi)下(xia)稱為“nmos晶(jing)(jing)體(ti)(ti)管”)qn1組成，這兩個(ge)晶(jing)(jing)體(ti)(ti)管串(chuan)聯(lian)(lian)耦(ou)合在低(di)電(dian)源電(dian)位(wei)(vdd)和(he)(he)(he)(he)地(di)(di)電(dian)位(wei)(gnd)之(zhi)間。pmos晶(jing)(jing)體(ti)(ti)管qp1的(de)(de)柵(zha)(zha)極(ji)和(he)(he)(he)(he)nmos晶(jing)(jing)體(ti)(ti)管qn1的(de)(de)柵(zha)(zha)極(ji)耦(ou)合至(zhi)輸入信(xin)號(hao)(in)。in是0v至(zhi)vdd的(de)(de)低(di)幅(fu)度信(xin)號(hao)。用(yong)作柵(zha)(zha)極(ji)控(kong)制電(dian)路(lu)的(de)(de)反(fan)(fan)相(xiang)(xiang)器(qi)(qi)inv2由pmos晶(jing)(jing)體(ti)(ti)管qp2和(he)(he)(he)(he)nmos晶(jing)(jing)體(ti)(ti)管qn2組成，這兩個(ge)晶(jing)(jing)體(ti)(ti)管串(chuan)聯(lian)(lian)耦(ou)合在低(di)電(dian)源電(dian)位(wei)(vdd)和(he)(he)(he)(he)地(di)(di)電(dian)位(wei)(gnd)之(zhi)間。pmos晶(jing)(jing)體(ti)(ti)管qp2的(de)(de)柵(zha)(zha)極(ji)和(he)(he)(he)(he)nmos晶(jing)(jing)體(ti)(ti)管qn2的(de)(de)柵(zha)(zha)極(ji)耦(ou)合至(zhi)反(fan)(fan)相(xiang)(xiang)信(xin)號(hao)(/in)。反(fan)(fan)相(xiang)(xiang)器(qi)(qi)inv2生成第一(yi)信(xin)號(hao)(in2)。

柵極控制電(dian)路(lu)gc生(sheng)成第二(er)信號(vg)。稍(shao)后將(jiang)描(miao)述細節。中間電(dian)位(wei)(wei)生(sheng)成電(dian)路(lu)ivg生(sheng)成第一(yi)電(dian)位(wei)(wei)(vrefp1)、第二(er)電(dian)位(wei)(wei)(vrefp2)和第三電(dian)位(wei)(wei)(vrefn)。稍(shao)后將(jiang)描(miao)述細節。

串(chuan)(chuan)聯電(dian)路sc由pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp1、pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp2、nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn2和(he)nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn1組成，這(zhe)些晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)串(chuan)(chuan)聯耦(ou)(ou)合(he)(he)在高電(dian)源電(dian)位(wei)(wei)(vpp)和(he)地電(dian)位(wei)(wei)(gnd)之間。第(di)(di)二信號(vg)被施加給pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp1的(de)(de)(de)(de)柵(zha)(zha)(zha)極(ji)(ji)。第(di)(di)一(yi)電(dian)位(wei)(wei)(vrefp1)被施加給pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp2的(de)(de)(de)(de)柵(zha)(zha)(zha)極(ji)(ji)。第(di)(di)二電(dian)位(wei)(wei)(vrefn)被施加給nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn2的(de)(de)(de)(de)柵(zha)(zha)(zha)極(ji)(ji)。作為反相(xiang)器inv2的(de)(de)(de)(de)輸出(chu)(chu)信號的(de)(de)(de)(de)第(di)(di)一(yi)信號(in2)被施加給nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn1的(de)(de)(de)(de)柵(zha)(zha)(zha)極(ji)(ji)。第(di)(di)二信號(vg)是具有電(dian)位(wei)(wei)vpp/2至(zhi)vpp的(de)(de)(de)(de)信號。第(di)(di)一(yi)電(dian)位(wei)(wei)(vrefp1)和(he)第(di)(di)三電(dian)位(wei)(wei)(vrefn)是約(yue)為vpp/2的(de)(de)(de)(de)電(dian)位(wei)(wei)。pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp1的(de)(de)(de)(de)襯底(di)電(dian)極(ji)(ji)耦(ou)(ou)合(he)(he)至(zhi)高電(dian)源電(dian)位(wei)(wei)(vpp)，并且nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn1的(de)(de)(de)(de)襯底(di)電(dian)極(ji)(ji)耦(ou)(ou)合(he)(he)至(zhi)地電(dian)位(wei)(wei)(gnd)。pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp2的(de)(de)(de)(de)襯底(di)電(dian)極(ji)(ji)耦(ou)(ou)合(he)(he)至(zhi)pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp2的(de)(de)(de)(de)源極(ji)(ji)。nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn2的(de)(de)(de)(de)襯底(di)電(dian)極(ji)(ji)耦(ou)(ou)合(he)(he)至(zhi)nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn2的(de)(de)(de)(de)源極(ji)(ji)。從(cong)pmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mp2與nmos晶(jing)(jing)(jing)(jing)(jing)(jing)體(ti)(ti)管(guan)(guan)(guan)mn2的(de)(de)(de)(de)連接節點得(de)到輸出(chu)(chu)信號(out)。

耦(ou)合在(zai)低(di)電(dian)(dian)源電(dian)(dian)位(wei)(vdd)和(he)地電(dian)(dian)位(wei)(gnd)之(zhi)間的(de)(de)晶(jing)體(ti)(ti)管以及耦(ou)合在(zai)高(gao)電(dian)(dian)源電(dian)(dian)位(wei)(vpp)與地電(dian)(dian)位(wei)(gnd)之(zhi)間的(de)(de)晶(jing)體(ti)(ti)管是在(zai)相同工藝中(zhong)形成的(de)(de)低(di)耐(nai)受(shou)電(dian)(dian)壓器件(jian)。換(huan)言之(zhi)，組(zu)成反相器inv的(de)(de)晶(jing)體(ti)(ti)管的(de)(de)耐(nai)受(shou)電(dian)(dian)壓和(he)組(zu)成串聯電(dian)(dian)路sc的(de)(de)晶(jing)體(ti)(ti)管的(de)(de)耐(nai)受(shou)電(dian)(dian)壓是相當的(de)(de)，并且每(mei)個(ge)晶(jing)體(ti)(ti)管的(de)(de)耐(nai)受(shou)電(dian)(dian)壓都高(gao)于vdd但低(di)于vpp。例如，vdd為(wei)1.8v，vpp為(wei)3.3v，以及gnd為(wei)0v。

圖(tu)(tu)2是示出柵(zha)極(ji)(ji)控制電(dian)(dian)路的電(dian)(dian)路圖(tu)(tu)。在柵(zha)極(ji)(ji)控制電(dian)(dian)路gc中，串(chuan)聯(lian)(lian)(lian)電(dian)(dian)路設置在高電(dian)(dian)源(yuan)電(dian)(dian)位(vpp)與地電(dian)(dian)位(gnd)之(zhi)間。串(chuan)聯(lian)(lian)(lian)電(dian)(dian)路由pmos晶(jing)體管mp11、pmos晶(jing)體管mp12(其柵(zha)極(ji)(ji)提供有(you)(you)第二電(dian)(dian)位(vrefp2))、nmos晶(jing)體管mn12(其柵(zha)極(ji)(ji)提供有(you)(you)第三電(dian)(dian)位(vrefn))和nmos晶(jing)體管mn11(其柵(zha)極(ji)(ji)提供有(you)(you)輸入信號(in))組成，這些(xie)晶(jing)體管均串(chuan)聯(lian)(lian)(lian)耦合。

此外，在柵(zha)極(ji)(ji)控制電(dian)路(lu)gc中，另(ling)一(yi)串聯電(dian)路(lu)設(she)置在高電(dian)源(yuan)電(dian)位(wei)(vpp)與地電(dian)位(wei)(gnd)之間(jian)。另(ling)一(yi)串聯電(dian)路(lu)由pmos晶體(ti)管mp13、pmos晶體(ti)管mp14(其(qi)柵(zha)極(ji)(ji)提(ti)供(gong)有第二(er)電(dian)位(wei)(vrefp2))、nmos晶體(ti)管mn14(其(qi)柵(zha)極(ji)(ji)提(ti)供(gong)有第三電(dian)位(wei)(vrefn))和nmos晶體(ti)管nm13(其(qi)柵(zha)極(ji)(ji)提(ti)供(gong)有反相信號(/in))組成，這(zhe)些晶體(ti)管都(dou)串聯耦合(he)。

pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp11的(de)(de)(de)(de)(de)(de)(de)(de)柵(zha)極(ji)(ji)(ji)(ji)耦(ou)(ou)(ou)合(he)(he)(he)至(zhi)(zhi)(zhi)節(jie)(jie)(jie)點(dian)n13，該節(jie)(jie)(jie)點(dian)是pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp13和(he)(he)(he)(he)pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp14的(de)(de)(de)(de)(de)(de)(de)(de)連接節(jie)(jie)(jie)點(dian)。pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp13的(de)(de)(de)(de)(de)(de)(de)(de)柵(zha)極(ji)(ji)(ji)(ji)耦(ou)(ou)(ou)合(he)(he)(he)至(zhi)(zhi)(zhi)節(jie)(jie)(jie)點(dian)n11，該節(jie)(jie)(jie)點(dian)是pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp11與pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp12的(de)(de)(de)(de)(de)(de)(de)(de)連接節(jie)(jie)(jie)點(dian)。同時，pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp11和(he)(he)(he)(he)mp13的(de)(de)(de)(de)(de)(de)(de)(de)襯底(di)電(dian)(dian)(dian)極(ji)(ji)(ji)(ji)耦(ou)(ou)(ou)合(he)(he)(he)至(zhi)(zhi)(zhi)vpp。nmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mn11和(he)(he)(he)(he)mn13的(de)(de)(de)(de)(de)(de)(de)(de)襯底(di)電(dian)(dian)(dian)極(ji)(ji)(ji)(ji)耦(ou)(ou)(ou)合(he)(he)(he)至(zhi)(zhi)(zhi)gnd。pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp12和(he)(he)(he)(he)mp14的(de)(de)(de)(de)(de)(de)(de)(de)襯底(di)電(dian)(dian)(dian)極(ji)(ji)(ji)(ji)分(fen)別耦(ou)(ou)(ou)合(he)(he)(he)至(zhi)(zhi)(zhi)pmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mp12和(he)(he)(he)(he)mp14的(de)(de)(de)(de)(de)(de)(de)(de)源(yuan)極(ji)(ji)(ji)(ji)。nmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mn12和(he)(he)(he)(he)mn14的(de)(de)(de)(de)(de)(de)(de)(de)襯底(di)電(dian)(dian)(dian)極(ji)(ji)(ji)(ji)分(fen)別耦(ou)(ou)(ou)合(he)(he)(he)至(zhi)(zhi)(zhi)nmos晶(jing)(jing)體(ti)(ti)(ti)(ti)管(guan)(guan)mn12和(he)(he)(he)(he)mn14的(de)(de)(de)(de)(de)(de)(de)(de)源(yuan)極(ji)(ji)(ji)(ji)。從耦(ou)(ou)(ou)合(he)(he)(he)至(zhi)(zhi)(zhi)節(jie)(jie)(jie)點(dian)n13的(de)(de)(de)(de)(de)(de)(de)(de)節(jie)(jie)(jie)點(dian)n4得到柵(zha)極(ji)(ji)(ji)(ji)電(dian)(dian)(dian)位(vg)。通過設置vrefp2＝vpp/2-|vtp|，vg稱(cheng)為位于vpp/2和(he)(he)(he)(he)vpp之間的(de)(de)(de)(de)(de)(de)(de)(de)幅(fu)度的(de)(de)(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)位。

通過相應柵極和(he)漏極的交叉耦合，鎖存電路(lu)lt由pmos晶體(ti)(ti)管mp11和(he)pmos晶體(ti)(ti)管mp13組成；相應地(di)，可以(yi)切斷靜止(zhi)電流(liu)(stationarycurrent)。

鉗位電(dian)(dian)路cl由pmos晶體管mp12和mp14以及nmos晶體管mn12和mn14組成。pmos晶體管mp11和mp13的(de)(de)(de)漏(lou)極電(dian)(dian)位通過鉗位電(dian)(dian)路cl的(de)(de)(de)動作僅(jin)下降到(dao)vrefp2。nmos晶體管mn11和mn13的(de)(de)(de)漏(lou)極電(dian)(dian)位通過鉗位電(dian)(dian)路cl的(de)(de)(de)動作僅(jin)上升到(dao)vrefn。

鎖存反相電路li由nmos晶(jing)體管mn11和mn13組(zu)成，鎖存電路lt的狀態(tai)可以基于輸入信號(in)和反相信號(/in)來反轉。

圖(tu)3是示出(chu)中間(jian)(jian)電(dian)(dian)位(wei)生成電(dian)(dian)路(lu)的(de)(de)電(dian)(dian)路(lu)圖(tu)。在(zai)中間(jian)(jian)電(dian)(dian)位(wei)生成電(dian)(dian)路(lu)ivg中，電(dian)(dian)阻(zu)元(yuan)(yuan)件(jian)r1和(he)(he)電(dian)(dian)阻(zu)元(yuan)(yuan)件(jian)r2串聯耦合在(zai)高電(dian)(dian)源電(dian)(dian)位(wei)(vpp)與地電(dian)(dian)位(wei)(gnd)之間(jian)(jian)，并且從電(dian)(dian)阻(zu)元(yuan)(yuan)件(jian)r1和(he)(he)電(dian)(dian)阻(zu)元(yuan)(yuan)件(jian)r2的(de)(de)連接節點得(de)到第一電(dian)(dian)位(wei)(vrefp1)和(he)(he)第三(san)電(dian)(dian)位(wei)(vrefn)。假設電(dian)(dian)阻(zu)元(yuan)(yuan)件(jian)r1的(de)(de)電(dian)(dian)阻(zu)值為(wei)r1且電(dian)(dian)阻(zu)元(yuan)(yuan)件(jian)r2的(de)(de)電(dian)(dian)阻(zu)值為(wei)r2，則第一電(dian)(dian)位(wei)(vrefp1)和(he)(he)第三(san)電(dian)(dian)位(wei)(vrefn)的(de)(de)值通(tong)過以下(xia)等式(shi)(1)給(gei)出(chu)。

vrefp1＝vrefn＝r2/(r1+r2)···(1)

在(zai)(zai)本實施例中，定義為vrefp1＝vrefn，然(ran)而，可(ke)以(yi)(yi)定義為vrefp1≠vrefn，只(zhi)要(yao)它(ta)們是vpp/2左(zuo)右的(de)電(dian)(dian)壓(ya)即(ji)可(ke)。在(zai)(zai)中間電(dian)(dian)位(wei)(wei)(wei)生成電(dian)(dian)路ivg中，電(dian)(dian)阻(zu)(zu)(zu)元件(jian)(jian)r3和(he)電(dian)(dian)阻(zu)(zu)(zu)元件(jian)(jian)r4串聯耦合在(zai)(zai)高電(dian)(dian)源電(dian)(dian)位(wei)(wei)(wei)(vpp)與地電(dian)(dian)位(wei)(wei)(wei)(gnd)之間，并且(qie)從(cong)電(dian)(dian)阻(zu)(zu)(zu)元件(jian)(jian)r3和(he)電(dian)(dian)阻(zu)(zu)(zu)元件(jian)(jian)r4的(de)連(lian)接節(jie)點得(de)到第(di)二電(dian)(dian)位(wei)(wei)(wei)(vrefp2)。假設電(dian)(dian)阻(zu)(zu)(zu)元件(jian)(jian)r3的(de)電(dian)(dian)阻(zu)(zu)(zu)值為r3且(qie)電(dian)(dian)阻(zu)(zu)(zu)元件(jian)(jian)r4的(de)電(dian)(dian)阻(zu)(zu)(zu)值為r4，則第(di)二電(dian)(dian)位(wei)(wei)(wei)(vrefp2)的(de)值通過以(yi)(yi)下等式(2)給出。

vrefp2＝r4/(r3+r4)···(2)

電阻元(yuan)件r1、r2、r3和r4可以通過pmos晶(jing)體管(guan)或nmos晶(jing)體管(guan)形成。

接下來(lai)，解(jie)釋操(cao)作。這里，假設“h”為(wei)低電源電位(vdd)，“hh”為(wei)高電源電位(vpp)，以及(ji)“l”是地(di)電位(gnd)。地(di)電位也稱為(wei)參(can)考電位。

首先，當輸入信號(hao)(hao)(in)為(wei)(wei)(wei)“l”時，節(jie)點(dian)(dian)(dian)n1變為(wei)(wei)(wei)“h”且(qie)nmos晶(jing)(jing)體(ti)管(guan)(guan)mn1截止。同時，柵(zha)極控制(zhi)電(dian)路gc的(de)輸出(chu)(chu)節(jie)點(dian)(dian)(dian)n4為(wei)(wei)(wei)vrefp2+|vtp|；相應地，如(ru)果(guo)(vpp-vrefp2-|vtp|)>|vtp|，則(ze)pmos晶(jing)(jing)體(ti)管(guan)(guan)mp1導通，并且(qie)作為(wei)(wei)(wei)pmos晶(jing)(jing)體(ti)管(guan)(guan)mp1和(he)pmos晶(jing)(jing)體(ti)管(guan)(guan)mp2的(de)連接節(jie)點(dian)(dian)(dian)的(de)節(jie)點(dian)(dian)(dian)n3被上拉至“hh”。如(ru)果(guo)(vpp-vrefp1)>|vtp|，則(ze)pmos晶(jing)(jing)體(ti)管(guan)(guan)mp2也導通，輸出(chu)(chu)信號(hao)(hao)(out)也設置為(wei)(wei)(wei)“hh”，并且(qie)作為(wei)(wei)(wei)nmos晶(jing)(jing)體(ti)管(guan)(guan)mn1和(he)nmos晶(jing)(jing)體(ti)管(guan)(guan)mn2的(de)連接節(jie)點(dian)(dian)(dian)的(de)節(jie)點(dian)(dian)(dian)n2經由nmos晶(jing)(jing)體(ti)管(guan)(guan)mn2被上拉至(vrefn-vtn)且(qie)穩定。

另一方(fang)面，當輸入(ru)信(xin)(xin)號(hao)(in)為“h”時(shi)，節(jie)點(dian)(dian)(dian)n1變為“l”，nmos晶體(ti)(ti)(ti)管(guan)mn1導通，并(bing)且(qie)作為nmos晶體(ti)(ti)(ti)管(guan)mn1和(he)nmos晶體(ti)(ti)(ti)管(guan)mn2的(de)連接節(jie)點(dian)(dian)(dian)的(de)節(jie)點(dian)(dian)(dian)n2被(bei)(bei)下(xia)拉(la)至(zhi)(zhi)“l”。如果vrefn>vtn，則nmos晶體(ti)(ti)(ti)管(guan)mn2也(ye)導通，并(bing)且(qie)輸出信(xin)(xin)號(hao)(out)也(ye)被(bei)(bei)設置為“l”。此外(wai)，輸出節(jie)點(dian)(dian)(dian)n4為“hh”。因此，pmos晶體(ti)(ti)(ti)管(guan)mp1截(jie)止，并(bing)且(qie)節(jie)點(dian)(dian)(dian)n3經由(you)pmos晶體(ti)(ti)(ti)管(guan)mp2被(bei)(bei)下(xia)拉(la)至(zhi)(zhi)(vrefp1+|vtp|)且(qie)穩定。

如上文所(suo)解(jie)釋(shi)的(de)(de)(de)(de)，根據圖1所(suo)示的(de)(de)(de)(de)比(bi)較示例，通過根據在(zai)(zai)(zai)vdd和(he)gnd之(zhi)間(jian)(jian)擺動的(de)(de)(de)(de)輸入信(xin)號(in)控制高電(dian)壓(ya)(ya)(ya)(ya)，可以(yi)得(de)到“l”和(he)“hh”的(de)(de)(de)(de)輸出信(xin)號(out)。在(zai)(zai)(zai)pmos晶體管(guan)(guan)mp1的(de)(de)(de)(de)漏(lou)(lou)極(ji)與(yu)源極(ji)之(zhi)間(jian)(jian)施(shi)加(jia)最高為(wei)(vpp-vrefp2-|vtp|)的(de)(de)(de)(de)電(dian)壓(ya)(ya)(ya)(ya)。在(zai)(zai)(zai)pmos晶體管(guan)(guan)mp2的(de)(de)(de)(de)漏(lou)(lou)極(ji)與(yu)源極(ji)之(zhi)間(jian)(jian)施(shi)加(jia)最高為(wei)(vrefp1+|vtp|)的(de)(de)(de)(de)電(dian)壓(ya)(ya)(ya)(ya)。在(zai)(zai)(zai)nmos晶體管(guan)(guan)mn1的(de)(de)(de)(de)漏(lou)(lou)極(ji)與(yu)源極(ji)之(zhi)間(jian)(jian)施(shi)加(jia)最高為(wei)(vrefn-vtn)的(de)(de)(de)(de)電(dian)壓(ya)(ya)(ya)(ya)。在(zai)(zai)(zai)nmos晶體管(guan)(guan)mn2的(de)(de)(de)(de)漏(lou)(lou)極(ji)與(yu)源極(ji)之(zhi)間(jian)(jian)施(shi)加(jia)最高為(wei)(vpp-vrefn+vtn)的(de)(de)(de)(de)電(dian)壓(ya)(ya)(ya)(ya)。通過將vrefp1和(he)vrefn設(she)置為(wei)約(yue)vpp/2的(de)(de)(de)(de)電(dian)壓(ya)(ya)(ya)(ya)，可以(yi)避免(mian)在(zai)(zai)(zai)mos晶體管(guan)(guan)的(de)(de)(de)(de)漏(lou)(lou)極(ji)和(he)源極(ji)之(zhi)間(jian)(jian)施(shi)加(jia)高電(dian)壓(ya)(ya)(ya)(ya)(vpp)的(de)(de)(de)(de)情(qing)況。

向(xiang)(xiang)pmos晶(jing)(jing)體(ti)管(guan)mp1的(de)(de)(de)柵極氧(yang)(yang)化(hua)(hua)物(wu)層(ceng)施加(jia)(jia)最高為(wei)(vpp-vrefp2-|vtp|)的(de)(de)(de)電壓(ya)。向(xiang)(xiang)pmos晶(jing)(jing)體(ti)管(guan)mp2的(de)(de)(de)柵極氧(yang)(yang)化(hua)(hua)物(wu)層(ceng)施加(jia)(jia)最高為(wei)(vpp-vrefp1)的(de)(de)(de)電壓(ya)。向(xiang)(xiang)nmos晶(jing)(jing)體(ti)管(guan)mn1的(de)(de)(de)柵極氧(yang)(yang)化(hua)(hua)物(wu)層(ceng)施加(jia)(jia)最高為(wei)vdd的(de)(de)(de)電壓(ya)。向(xiang)(xiang)nmos晶(jing)(jing)體(ti)管(guan)mn2的(de)(de)(de)柵極氧(yang)(yang)化(hua)(hua)物(wu)層(ceng)施加(jia)(jia)最高為(wei)vrefn的(de)(de)(de)電壓(ya)。通過將vrefp1和vrefn設置為(wei)約(yue)vpp/2的(de)(de)(de)電壓(ya)，可以避免向(xiang)(xiang)mos晶(jing)(jing)體(ti)管(guan)的(de)(de)(de)柵極氧(yang)(yang)化(hua)(hua)物(wu)層(ceng)施加(jia)(jia)強電場(chang)的(de)(de)(de)情況。

根(gen)據這些(xie)器件，變(bian)得不需要制(zhi)造具(ju)有高耐受電壓結構(gou)的pmos晶體管(guan)mp1和(he)mp2以及nmos晶體管(guan)mn1和(he)mn2。因此(ci)，可(ke)以緩解制(zhi)造工藝變(bian)得復雜(za)且(qie)生產成本增加(jia)的問題。

然(ran)而，當輸(shu)出信號(out)從“hh”變(bian)為“l”時(shi)(shi)，反相(xiang)器inv2的輸(shu)出信號(in2)變(bian)為“h”；相(xiang)應地，vgsn1變(bian)為vgsn1＝vdd。節點n2的電(dian)位變(bian)為vdsn1。通(tong)過(guo)vrefn-vdsn1給出vgsn2，并且當vrefn＝vpp/2時(shi)(shi)得到(dao)(dao)vgsn2＝vpp/2-vdsn1。當作為實際使(shi)用(yong)的示例(li)假設vpp＝3.3v且vdd＝1.8v時(shi)(shi)，通(tong)過(guo)vgsn2＝1.65v-vdsn1且vgsn1＝1.8v給出vgsn2和vgsn1，并且得到(dao)(dao)vgsn2<vgsn1。因(yin)此，nmos晶(jing)體(ti)管mn2的導通(tong)阻抗(kang)變(bian)得大(da)于nmos晶(jing)體(ti)管mn1的導通(tong)阻抗(kang)，并且得到(dao)(dao)vdsn2>vdsn1。因(yin)此，nmos晶(jing)體(ti)管mn2的漏極(ji)-源(yuan)極(ji)電(dian)壓(ya)變(bian)大(da)。通(tong)過(guo)vdsn2＝vpp-vdsn1＝3.3v-vdsn1＝1.8v+1.5v-vdsn1＝vdd+1.5v-vdsn1給出vdsn2，并且當vdsn1變(bian)為vdsn1<1.5v時(shi)(shi)，得到(dao)(dao)vdsn2>vdd。

當(dang)(dang)輸(shu)出信號(hao)(out)從(cong)“l”變為(wei)(wei)(wei)“hh”時，節點n4處于(yu)vrefp2+|vtp|，并(bing)且(qie)(qie)(qie)得(de)到(dao)(dao)vgsp1＝vpp-vrefp2-|vtp|。當(dang)(dang)vrefp2＝vpp/2-|vtp|時，得(de)到(dao)(dao)vgsp1＝vpp/2。節點n3的電位(wei)變為(wei)(wei)(wei)vpp-vdsp1。通(tong)(tong)過(vpp-vdsp1)-vrefp1給(gei)出vgsp2，并(bing)且(qie)(qie)(qie)當(dang)(dang)vrefp1＝vpp/2時得(de)到(dao)(dao)vgsp2＝vpp/2-vdsp1。當(dang)(dang)作為(wei)(wei)(wei)實(shi)際使(shi)用的示例假設vpp＝3.3v且(qie)(qie)(qie)vdd＝1.8v時，通(tong)(tong)過vgsp2＝1.65v-vdsp1且(qie)(qie)(qie)vgsp1＝1.65v給(gei)出vgsp2和vgsp1，并(bing)且(qie)(qie)(qie)得(de)到(dao)(dao)vdsp1>0v；因(yin)此，得(de)到(dao)(dao)vgsp2<vgsp1。因(yin)此，pmos晶體管mp2的導通(tong)(tong)阻抗變得(de)大于(yu)pmos晶體管mp1的導通(tong)(tong)阻抗，并(bing)且(qie)(qie)(qie)得(de)到(dao)(dao)vdsp2>vdsp1。因(yin)此，pmos晶體管mp2的漏極-源極電壓變大。通(tong)(tong)過vdsp2＝vpp-vdsp1＝3.3v-vdsp1＝1.8v+1.5v-vdsp1＝vdd+1.5v-vdsp1給(gei)出vdsp2，并(bing)且(qie)(qie)(qie)當(dang)(dang)vdsp1<1.5v時，得(de)到(dao)(dao)vdsp2>vdd。

一般地，通過以下等式(3)表(biao)示熱載(zai)子(hci)劣化與(yu)vds之間的關系。

即，當vdsn2較大時，nmos晶體管(guan)mn2的熱載子劣化指數(shu)級(ji)增加。具體地，在上(shang)述電(dian)路中，采(cai)用(yong)低耐受電(dian)壓(ya)(ya)晶體管(guan)，并且輸出高幅度的電(dian)壓(ya)(ya)。因此，超(chao)過vdd的vds可以如上(shang)文(wen)所述施加，并且劣化變得嚴重。

<實施例>

使vgsn1較低的裝置(使反相器inv的輸出電位變低的電位轉換電路)設置在作為柵極控制電路的反相器inv與n溝道mos晶體管mn1的柵極之間。使vgsp1較低的裝置(使柵極控制電路gc的輸出電位變高的電位轉換電路)設置在柵極控制電路gc與p溝道mos晶體管mp1的柵極之間。因此，當設置為且時，得到vdsn1≈vdsn2≈vpp/2＝1.65v<1.8v＝vdd且vdsp1≈vdsp2≈vpp/2＝1.65v<1.8v＝vd。因此，可以使vdsn2和(he)vdsp2變低。

(實施例1)

圖4是(shi)示出根據實施例1的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移(yi)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)圖。電(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移(yi)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)ls1與電(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移(yi)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)lsr相(xiang)同，除了(le)在反相(xiang)器(qi)(qi)inv2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)輸(shu)(shu)出與nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn1的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)柵(zha)(zha)(zha)極(ji)(ji)(ji)(ji)(ji)之間添加了(le)電(dian)(dian)(dian)(dian)位(wei)(wei)(wei)轉換電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)cv1。電(dian)(dian)(dian)(dian)位(wei)(wei)(wei)轉換電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)cv1由(you)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)qn3(nmos傳輸(shu)(shu)門)組成。nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)qn3將(jiang)輸(shu)(shu)出電(dian)(dian)(dian)(dian)位(wei)(wei)(wei)與輸(shu)(shu)入(ru)電(dian)(dian)(dian)(dian)位(wei)(wei)(wei)分離。vdd被(bei)(bei)施加至(zhi)(zhi)(zhi)(zhi)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)qn3的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)柵(zha)(zha)(zha)極(ji)(ji)(ji)(ji)(ji)，并(bing)(bing)(bing)且nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)qn3的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn1的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)柵(zha)(zha)(zha)極(ji)(ji)(ji)(ji)(ji)(節(jie)點n7)。反相(xiang)器(qi)(qi)inv2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)輸(shu)(shu)出的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)幅度為(wei)0-vdd，并(bing)(bing)(bing)且經由(you)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)qn3的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)節(jie)點n7的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)過渡狀態(tai)的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)幅度在0和(he)(he)(vdd-vtn)之間。這里，vtn是(shi)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)qn3的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)閾(yu)值。因此，當nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn1導(dao)通(tong)時(shi)，vgsn1變(bian)(bian)為(wei)vdd-vtn，其比比較示例小(xiao)vtn。當vgsn1變(bian)(bian)小(xiao)時(shi)，nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn1的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)導(dao)通(tong)阻抗變(bian)(bian)大(da)，并(bing)(bing)(bing)且vdsn1變(bian)(bian)大(da)。通(tong)過nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn1和(he)(he)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)細分(subdivided)電(dian)(dian)(dian)(dian)壓來(lai)判定節(jie)點n2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)(dian)位(wei)(wei)(wei)。因此，當vdsn1變(bian)(bian)大(da)時(shi)，vdsn2變(bian)(bian)小(xiao)。根據上述等式(shi)(3)的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)關系，當vdsn2變(bian)(bian)小(xiao)時(shi)，nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)熱載(zai)子劣化可(ke)(ke)以(yi)(yi)(yi)被(bei)(bei)抑制(zhi)。在串聯(lian)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)sc中，pmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mp2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)pmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mp2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)源極(ji)(ji)(ji)(ji)(ji)，并(bing)(bing)(bing)且nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)源極(ji)(ji)(ji)(ji)(ji)。然而，可(ke)(ke)以(yi)(yi)(yi)進行配(pei)置，使得pmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mp2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)高電(dian)(dian)(dian)(dian)源電(dian)(dian)(dian)(dian)位(wei)(wei)(wei)(vpp)，并(bing)(bing)(bing)且nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)mn2的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)地電(dian)(dian)(dian)(dian)位(wei)(wei)(wei)(gnd)。串聯(lian)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)結構的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)修改也可(ke)(ke)以(yi)(yi)(yi)應(ying)用于以(yi)(yi)(yi)下(xia)實施例2-5。在柵(zha)(zha)(zha)極(ji)(ji)(ji)(ji)(ji)控制(zhi)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)gc中，pmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mp12和(he)(he)mp14的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)分別耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)pmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mp12和(he)(he)mp14的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)源極(ji)(ji)(ji)(ji)(ji)，并(bing)(bing)(bing)且nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn12和(he)(he)mn14的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)分別耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn12和(he)(he)mn14的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)源極(ji)(ji)(ji)(ji)(ji)。然而，可(ke)(ke)以(yi)(yi)(yi)進行配(pei)置，使得pmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mp12和(he)(he)mp14的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)分別耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)vpp，并(bing)(bing)(bing)且nmos晶(jing)(jing)(jing)(jing)(jing)體(ti)(ti)(ti)(ti)(ti)管(guan)(guan)(guan)(guan)(guan)(guan)(guan)(guan)mn12和(he)(he)mn14的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)襯(chen)(chen)(chen)(chen)底(di)電(dian)(dian)(dian)(dian)極(ji)(ji)(ji)(ji)(ji)分別耦(ou)合(he)至(zhi)(zhi)(zhi)(zhi)gnd。柵(zha)(zha)(zha)極(ji)(ji)(ji)(ji)(ji)控制(zhi)電(dian)(dian)(dian)(dian)路(lu)(lu)(lu)的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)結構的(de)(de)(de)(de)(de)(de)(de)(de)(de)(de)修改還可(ke)(ke)以(yi)(yi)(yi)應(ying)用于以(yi)(yi)(yi)下(xia)實施例2-5。

圖5是示出(chu)(chu)(chu)根據(ju)實施(shi)例1的(de)(de)(de)(de)半(ban)導(dao)體器(qi)件(jian)(jian)的(de)(de)(de)(de)框圖。半(ban)導(dao)體器(qi)件(jian)(jian)50包(bao)括(kuo)作為半(ban)導(dao)體器(qi)件(jian)(jian)的(de)(de)(de)(de)soc51和(he)(he)(he)電(dian)(dian)(dian)源ic52。soc51包(bao)括(kuo)位于一個半(ban)導(dao)體襯底(半(ban)導(dao)體芯片)上的(de)(de)(de)(de)內(nei)部電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)53以及(ji)i/o電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)54和(he)(he)(he)55。針對i/o電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)54和(he)(he)(he)55的(de)(de)(de)(de)輸出(chu)(chu)(chu)電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)采用電(dian)(dian)(dian)平位移電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)ls1。在本實施(shi)例中，i/o電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)54操作為輸出(chu)(chu)(chu)電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)，并且i/o電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)55操作為輸入電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)和(he)(he)(he)輸出(chu)(chu)(chu)電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)。從電(dian)(dian)(dian)源ic52向soc51的(de)(de)(de)(de)i/o電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)54和(he)(he)(he)55提供(gong)高電(dian)(dian)(dian)源電(dian)(dian)(dian)位(vpp＝3.3v)和(he)(he)(he)低電(dian)(dian)(dian)源電(dian)(dian)(dian)位(vdd)。從內(nei)部電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)53輸出(chu)(chu)(chu)的(de)(de)(de)(de)信(xin)號(hao)具有位于0v和(he)(he)(he)vdd之(zhi)(zhi)間(jian)的(de)(de)(de)(de)幅度，并且被提供(gong)給i/o電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)54和(he)(he)(he)55。0v和(he)(he)(he)vdd之(zhi)(zhi)間(jian)的(de)(de)(de)(de)幅度的(de)(de)(de)(de)信(xin)號(hao)通過i/o電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)54和(he)(he)(he)55的(de)(de)(de)(de)電(dian)(dian)(dian)平位移電(dian)(dian)(dian)路(lu)(lu)(lu)(lu)(lu)ls1轉換為0v和(he)(he)(he)vpp之(zhi)(zhi)間(jian)的(de)(de)(de)(de)信(xin)號(hao)，并且被輸出(chu)(chu)(chu)至soc51的(de)(de)(de)(de)外部。

(實施例2)

圖6是示(shi)出根(gen)據(ju)實(shi)(shi)施(shi)例(li)2的(de)電(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)的(de)電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)圖。根(gen)據(ju)實(shi)(shi)施(shi)例(li)2的(de)電(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)ls2滿足(zu)當(dang)(dang)高(gao)(gao)電(dian)(dian)(dian)(dian)(dian)源電(dian)(dian)(dian)(dian)(dian)位(wei)(wei)(vpp)較(jiao)高(gao)(gao)時(shi)的(de)熱(re)載子劣(lie)化的(de)抑制(zhi)以及(ji)當(dang)(dang)vpp較(jiao)低(di)(di)(到不超過mos晶(jing)(jing)體(ti)管(guan)的(de)耐(nai)受(shou)電(dian)(dian)(dian)(dian)(dian)壓的(de)程(cheng)度(du))時(shi)的(de)高(gao)(gao)速操(cao)(cao)作(zuo)(zuo)。電(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)ls2與電(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)ls1相同(tong)，除了電(dian)(dian)(dian)(dian)(dian)位(wei)(wei)轉換(huan)電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)。電(dian)(dian)(dian)(dian)(dian)位(wei)(wei)轉換(huan)電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)cv2包括與nmos晶(jing)(jing)體(ti)管(guan)qn3并(bing)(bing)行耦合的(de)pmos晶(jing)(jing)體(ti)管(guan)qp3(pmos傳輸門)。poc信(xin)號被(bei)施(shi)加給(gei)pmos晶(jing)(jing)體(ti)管(guan)qp3的(de)柵極(ji)，并(bing)(bing)且(qie)(qie)(qie)pmos晶(jing)(jing)體(ti)管(guan)qp3的(de)襯(chen)底電(dian)(dian)(dian)(dian)(dian)極(ji)耦合至反相器inv2的(de)輸出。當(dang)(dang)vpp較(jiao)高(gao)(gao)時(shi)，poc信(xin)號被(bei)設置為(wei)(wei)“h”(vdd)，并(bing)(bing)且(qie)(qie)(qie)pmos晶(jing)(jing)體(ti)管(guan)qp3截止。在(zai)這種情(qing)況下，電(dian)(dian)(dian)(dian)(dian)路(lu)(lu)操(cao)(cao)作(zuo)(zuo)與實(shi)(shi)施(shi)例(li)1相同(tong)。當(dang)(dang)節(jie)點(dian)n7的(de)“h”電(dian)(dian)(dian)(dian)(dian)平變(bian)為(wei)(wei)(vdd-vtn)時(shi)，可(ke)以如實(shi)(shi)施(shi)例(li)1一樣抑制(zhi)nmos晶(jing)(jing)體(ti)管(guan)qn2的(de)熱(re)載子劣(lie)化。當(dang)(dang)vpp較(jiao)低(di)(di)時(shi)，poc信(xin)號被(bei)設置為(wei)(wei)“l”(gnd)，并(bing)(bing)且(qie)(qie)(qie)pmos晶(jing)(jing)體(ti)管(guan)qp3導通。因(yin)此，節(jie)點(dian)n7的(de)“h”電(dian)(dian)(dian)(dian)(dian)平變(bian)為(wei)(wei)vdd，并(bing)(bing)且(qie)(qie)(qie)幅度(du)在(zai)0v和vdd之間(jian)；相應地(di)，高(gao)(gao)速操(cao)(cao)作(zuo)(zuo)變(bian)得可(ke)能。

圖7是(shi)示(shi)出(chu)(chu)根(gen)據(ju)實施(shi)例(li)2的(de)信(xin)息(xi)設備的(de)框圖。信(xin)息(xi)設備70包(bao)括作為(wei)半導(dao)體器(qi)件的(de)soc71、電(dian)(dian)源ic72和(he)sd存儲卡76。soc71包(bao)括位(wei)于(yu)一(yi)個半導(dao)體襯底(半導(dao)體芯片)之上的(de)sd主機(ji)(ji)控制(zhi)器(qi)73以(yi)(yi)及(ji)i/o電(dian)(dian)路(lu)(lu)(lu)74和(he)75。sd主機(ji)(ji)控制(zhi)器(qi)73用于(yu)在(zai)cpu(未示(shi)出(chu)(chu))與sd存儲卡76之間交換數(shu)據(ju)和(he)控制(zhi)信(xin)號(hao)，例(li)如輸(shu)(shu)出(chu)(chu)時鐘(zhong)信(xin)號(hao)(clk)和(he)命令(cmd)，并(bing)(bing)且(qie)發送和(he)接收(shou)數(shu)據(ju)(dat)。針(zhen)對i/o電(dian)(dian)路(lu)(lu)(lu)74和(he)75的(de)輸(shu)(shu)出(chu)(chu)電(dian)(dian)路(lu)(lu)(lu)采(cai)用電(dian)(dian)平位(wei)移電(dian)(dian)路(lu)(lu)(lu)ls2。在(zai)本實施(shi)例(li)中，i/o電(dian)(dian)路(lu)(lu)(lu)74操作為(wei)輸(shu)(shu)出(chu)(chu)電(dian)(dian)路(lu)(lu)(lu)，并(bing)(bing)且(qie)i/o電(dian)(dian)路(lu)(lu)(lu)75操作為(wei)輸(shu)(shu)入電(dian)(dian)路(lu)(lu)(lu)和(he)輸(shu)(shu)出(chu)(chu)電(dian)(dian)路(lu)(lu)(lu)。從(cong)電(dian)(dian)源ic72向soc71的(de)i/o電(dian)(dian)路(lu)(lu)(lu)74和(he)75提(ti)供高電(dian)(dian)源電(dian)(dian)位(wei)(vpp＝3.3v或(huo)1.8v)。從(cong)電(dian)(dian)源ic72向sd主機(ji)(ji)控制(zhi)器(qi)73以(yi)(yi)及(ji)i/o電(dian)(dian)路(lu)(lu)(lu)74和(he)75提(ti)供低電(dian)(dian)源電(dian)(dian)位(wei)(vdd＝1.8v)。電(dian)(dian)源ic72在(zai)poc信(xin)號(hao)為(wei)“l”時提(ti)供1.8v，以(yi)(yi)及(ji)在(zai)poc信(xin)號(hao)為(wei)“h”時提(ti)供3.3v。從(cong)sd主機(ji)(ji)控制(zhi)器(qi)73輸(shu)(shu)出(chu)(chu)的(de)信(xin)號(hao)具有(you)0v和(he)vdd之間的(de)幅度，并(bing)(bing)且(qie)被提(ti)供給(gei)i/o電(dian)(dian)路(lu)(lu)(lu)74和(he)75。電(dian)(dian)源ic72可以(yi)(yi)在(zai)soc71中構建。

soc71與sd存儲(chu)卡(ka)76之(zhi)間的(de)(de)信號的(de)(de)交換使(shi)(shi)用(yong)兩種模式：3.3v電(dian)(dian)(dian)(dian)(dian)平(ping)(ping)和1.8v電(dian)(dian)(dian)(dian)(dian)平(ping)(ping)。在(zai)3.3v電(dian)(dian)(dian)(dian)(dian)平(ping)(ping)上(shang)(shang)執(zhi)(zhi)行(xing)(xing)(xing)低速(su)操(cao)作(zuo)以(yi)及在(zai)1.8v電(dian)(dian)(dian)(dian)(dian)平(ping)(ping)上(shang)(shang)執(zhi)(zhi)行(xing)(xing)(xing)高(gao)(gao)速(su)操(cao)作(zuo)。例如，根據sd存儲(chu)卡(ka)標準3.0，當電(dian)(dian)(dian)(dian)(dian)源(yuan)電(dian)(dian)(dian)(dian)(dian)壓為3.3v時，在(zai)50mhz的(de)(de)最大(da)頻率(lv)下(xia)執(zhi)(zhi)行(xing)(xing)(xing)操(cao)作(zuo)，以(yi)及當電(dian)(dian)(dian)(dian)(dian)源(yuan)電(dian)(dian)(dian)(dian)(dian)壓為1.8v時，在(zai)208mhz的(de)(de)最大(da)頻率(lv)下(xia)執(zhi)(zhi)行(xing)(xing)(xing)操(cao)作(zuo)。因此，對于(yu)1.8v處(chu)的(de)(de)電(dian)(dian)(dian)(dian)(dian)源(yuan)電(dian)(dian)(dian)(dian)(dian)壓來說，更(geng)加要(yao)求高(gao)(gao)速(su)操(cao)作(zuo)。從電(dian)(dian)(dian)(dian)(dian)源(yuan)ic72向soc71的(de)(de)電(dian)(dian)(dian)(dian)(dian)源(yuan)電(dian)(dian)(dian)(dian)(dian)位(wei)(vpp)提供3.3v或1.8v。通過(guo)soc71側上(shang)(shang)的(de)(de)poc信號來執(zhi)(zhi)行(xing)(xing)(xing)電(dian)(dian)(dian)(dian)(dian)源(yuan)ic72的(de)(de)輸出電(dian)(dian)(dian)(dian)(dian)源(yuan)電(dian)(dian)(dian)(dian)(dian)位(wei)在(zai)3.3v和1.8v之(zhi)間的(de)(de)切(qie)換。還通過(guo)控制信號poc來執(zhi)(zhi)行(xing)(xing)(xing)i/o電(dian)(dian)(dian)(dian)(dian)路74和75的(de)(de)3.3v電(dian)(dian)(dian)(dian)(dian)平(ping)(ping)與1.8v電(dian)(dian)(dian)(dian)(dian)平(ping)(ping)之(zhi)間的(de)(de)操(cao)作(zuo)模式的(de)(de)切(qie)換。在(zai)1.8v電(dian)(dian)(dian)(dian)(dian)平(ping)(ping)下(xia)，切(qie)換電(dian)(dian)(dian)(dian)(dian)路，使(shi)(shi)得i/o電(dian)(dian)(dian)(dian)(dian)路74和75可以(yi)執(zhi)(zhi)行(xing)(xing)(xing)高(gao)(gao)速(su)操(cao)作(zuo)。

(實施例3)

圖(tu)8是示出(chu)根據(ju)實施例3的(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)的(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)圖(tu)。根據(ju)實施例3的(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)ls3抑(yi)(yi)制pmos晶(jing)體管(guan)的(de)(de)(de)(de)(de)(de)熱(re)載子。電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)ls3與(yu)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)lsr相(xiang)同(tong)，除了(le)在柵(zha)極(ji)控制電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)gc與(yu)pmos晶(jing)體管(guan)mp1之(zhi)間(jian)(jian)添加電(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)(wei)轉換電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)cv3。電(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)(wei)轉換電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)cv3由pmos晶(jing)體管(guan)qp4(pmos傳輸(shu)門)組成，并(bing)(bing)且將輸(shu)出(chu)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)(wei)與(yu)輸(shu)入電(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)(wei)分(fen)離(li)。vdd被施加給pmos晶(jing)體管(guan)qp4的(de)(de)(de)(de)(de)(de)柵(zha)極(ji)，并(bing)(bing)且pmos晶(jing)體管(guan)qp4的(de)(de)(de)(de)(de)(de)襯底(di)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)極(ji)耦(ou)合至pmos晶(jing)體管(guan)mp1的(de)(de)(de)(de)(de)(de)柵(zha)極(ji)(節點(dian)(dian)n8)。因此，節點(dian)(dian)n8的(de)(de)(de)(de)(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平在(vpp/2+vtp)和vpp之(zhi)間(jian)(jian)。因此，vgsp1變小且vdsp1變大(da)。當vdsp1變大(da)時，vdsp2變小，并(bing)(bing)且pmos晶(jing)體管(guan)mp2的(de)(de)(de)(de)(de)(de)熱(re)載子劣(lie)化被抑(yi)(yi)制。與(yu)實施例1相(xiang)同(tong)，針對soc51的(de)(de)(de)(de)(de)(de)i/o電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)54和55采用電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)移(yi)(yi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)ls3。

(實施例4)

圖9是(shi)示出(chu)根據實施(shi)(shi)例(li)4的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)圖。根據實施(shi)(shi)例(li)4的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)ls4滿足當(dang)高(gao)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)源電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)(wei)(wei)(vpp)為(wei)高(gao)時熱載(zai)子劣化的(de)(de)抑(yi)制(zhi)以(yi)及當(dang)vpp為(wei)低(達到不超過mos晶(jing)(jing)體(ti)管(guan)的(de)(de)耐(nai)受電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓的(de)(de)程度(du))時的(de)(de)高(gao)速操作(zuo)。電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)ls4與(yu)(yu)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)ls3相(xiang)(xiang)同(tong)，除了電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)(wei)(wei)轉換(huan)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)。電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)位(wei)(wei)(wei)轉換(huan)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)cv4包括與(yu)(yu)pmos晶(jing)(jing)體(ti)管(guan)qp4并行耦合(he)的(de)(de)nmos晶(jing)(jing)體(ti)管(guan)qn4(nmos傳輸(shu)門)。/poc信號(hao)(hao)被(bei)(bei)施(shi)(shi)加給(gei)nmos晶(jing)(jing)體(ti)管(guan)qn4的(de)(de)柵極，并且pmos晶(jing)(jing)體(ti)管(guan)qp4的(de)(de)襯(chen)底電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)極耦合(he)至(zhi)柵極控制(zhi)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)gc的(de)(de)輸(shu)出(chu)(節點(dian)n4)。當(dang)vpp為(wei)高(gao)時，/poc信號(hao)(hao)被(bei)(bei)設(she)置為(wei)“l”(gnd)，并且nmos晶(jing)(jing)體(ti)管(guan)qn4截止。在(zai)這種(zhong)情(qing)況下，電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)操作(zuo)與(yu)(yu)實施(shi)(shi)例(li)3相(xiang)(xiang)同(tong)，并且節點(dian)n8的(de)(de)“l”電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平變(bian)為(wei)(vpp/2+vtp)；相(xiang)(xiang)應地，可以(yi)如實施(shi)(shi)例(li)3抑(yi)制(zhi)pmos晶(jing)(jing)體(ti)管(guan)mp2的(de)(de)熱載(zai)子劣化。當(dang)vpp為(wei)低時，/poc信號(hao)(hao)被(bei)(bei)設(she)置為(wei)“h”(vdd)，并且nmos晶(jing)(jing)體(ti)管(guan)qn4導通。因此(ci)，節點(dian)n8的(de)(de)“l”電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平變(bian)為(wei)vpp/2且且幅度(du)在(zai)vpp/2與(yu)(yu)vpp之間；相(xiang)(xiang)應地，高(gao)速操作(zuo)變(bian)得(de)可能。與(yu)(yu)實施(shi)(shi)例(li)2一樣，針對soc71的(de)(de)i/o電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)74和75采用電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)平位(wei)(wei)(wei)移電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)ls4。在(zai)這種(zhong)情(qing)況下，/poc信號(hao)(hao)被(bei)(bei)輸(shu)入(ru)至(zhi)i/o電(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)(dian)路(lu)(lu)(lu)74和75。

(實施例5)

圖(tu)(tu)10是根(gen)據實(shi)(shi)施(shi)(shi)例5的(de)電(dian)(dian)平位(wei)移電(dian)(dian)路(lu)的(de)電(dian)(dian)路(lu)圖(tu)(tu)。根(gen)據實(shi)(shi)施(shi)(shi)例5的(de)電(dian)(dian)平位(wei)移電(dian)(dian)路(lu)ls5滿足當高(gao)電(dian)(dian)源電(dian)(dian)位(wei)(vpp)為高(gao)時pmos晶體管(guan)mp2和(he)nmos晶體管(guan)mn2的(de)熱載(zai)子劣化的(de)抑制以(yi)及當vpp為低(達到不超過mos晶體管(guan)的(de)耐受電(dian)(dian)壓的(de)程度(du))時的(de)高(gao)速操(cao)作(zuo)。電(dian)(dian)平位(wei)移電(dian)(dian)路(lu)ls5是實(shi)(shi)施(shi)(shi)例2與(yu)實(shi)(shi)施(shi)(shi)例4結(jie)合的(de)電(dian)(dian)路(lu)，并且操(cao)作(zuo)與(yu)實(shi)(shi)施(shi)(shi)例2和(he)實(shi)(shi)施(shi)(shi)例4的(de)操(cao)作(zuo)相同。與(yu)實(shi)(shi)施(shi)(shi)例2相同，針對soc71的(de)i/o電(dian)(dian)路(lu)74和(he)75采(cai)用電(dian)(dian)平位(wei)移電(dian)(dian)路(lu)ls5。在這種情(qing)況下，poc信號和(he)/poc信號被輸入至i/o電(dian)(dian)路(lu)74和(he)75。

在不采(cai)用(yong)高(gao)耐受(shou)電(dian)壓(ya)結構的(de)(de)(de)(de)(de)(de)晶(jing)(jing)體管并(bing)防止過量電(dian)壓(ya)被(bei)施加給晶(jing)(jing)體管的(de)(de)(de)(de)(de)(de)柵極氧(yang)化(hua)物層(ceng)的(de)(de)(de)(de)(de)(de)情況(kuang)下，實施例采(cai)用(yong)根據低幅度(0v-vdd)的(de)(de)(de)(de)(de)(de)邏輯信號的(de)(de)(de)(de)(de)(de)輸入來輸出(chu)高(gao)幅度(0v-vpp)的(de)(de)(de)(de)(de)(de)信號的(de)(de)(de)(de)(de)(de)電(dian)路，其中輸出(chu)部分(fen)配置有分(fen)別串聯耦(ou)合(he)的(de)(de)(de)(de)(de)(de)pmos晶(jing)(jing)體管的(de)(de)(de)(de)(de)(de)多級和nmos晶(jing)(jing)體管的(de)(de)(de)(de)(de)(de)多級。

在實施(shi)例1、2和5中，通過在nmos晶(jing)體(ti)管的柵極與(yu)柵極控制(zhi)(zhi)電(dian)(dian)路之間(jian)耦合傳輸門，適當(dang)(dang)地控制(zhi)(zhi)施(shi)加給(gei)每個垂直堆(dui)疊的nmos晶(jing)體(ti)管的vds(漏極-源極電(dian)(dian)壓(ya))，并且在高電(dian)(dian)源電(dian)(dian)位(vpp)為(wei)(wei)高時(shi)抑制(zhi)(zhi)nmos晶(jing)體(ti)管的熱載子劣化。同時(shi)，在實施(shi)例2和5中，當(dang)(dang)vpp為(wei)(wei)低時(shi)實現高速操作(zuo)。

在實施(shi)(shi)例3、4和5中，通(tong)過在pmos晶(jing)體管(guan)的柵(zha)極(ji)(ji)與柵(zha)極(ji)(ji)控制(zhi)電路之間(jian)耦合傳輸門，適當(dang)地控制(zhi)施(shi)(shi)加給每(mei)個垂直堆疊的pmos晶(jing)體管(guan)的vds(漏極(ji)(ji)-源極(ji)(ji)電壓)，并且當(dang)高電源電位(vpp)為(wei)高時抑(yi)制(zhi)pmos晶(jing)體管(guan)的熱(re)載(zai)子劣化。同(tong)時，在實施(shi)(shi)例4和5中，當(dang)vpp為(wei)低(di)時實現高速操(cao)作。

根(gen)據實施例(li)可以增強使用低(di)耐受電(dian)壓器件的(de)(de)(de)高壓輸(shu)出電(dian)路(lu)的(de)(de)(de)可靠(kao)性。這尤其在(zai)引發(fa)可靠(kao)性的(de)(de)(de)顯著降低(di)的(de)(de)(de)小(xiao)型化的(de)(de)(de)最先(xian)進工藝中更(geng)加(jia)(jia)有效。隨著工藝朝向進一(yi)步的(de)(de)(de)小(xiao)型化行(xing)進，由于熱(re)載子而引起的(de)(de)(de)晶體管性能的(de)(de)(de)劣化變得更(geng)加(jia)(jia)顯著。

如(ru)上所(suo)述，本(ben)(ben)發(fa)明的(de)發(fa)明人完成的(de)發(fa)明基(ji)于(yu)實施例(li)進行(xing)了(le)具(ju)體的(de)說(shuo)明。然而，這不能強調說(shuo)本(ben)(ben)發(fa)明限于(yu)上述實施例(li)，在不背離(li)精神的(de)范(fan)圍中可(ke)以進行(xing)各種變化。

實施例1和(he)(he)實施例3可以組合(he)以采(cai)用電(dian)位轉換電(dian)路(lu)cv1和(he)(he)電(dian)位轉換電(dian)路(lu)cv3二者。

實(shi)施例1和5是輸出驅(qu)動器的示(shi)例。然而，同(tong)樣的技術(shu)可以(yi)類似地應(ying)用于晶(jing)體管被垂直堆(dui)疊且柵(zha)極偏置被控制的電路，從而耐(nai)受高電壓。