本發明涉及(ji)低(di)電壓差分信號(hao)傳(chuan)送器，尤其涉及(ji)使低(di)電壓差分信號(hao)傳(chuan)送器具有對工藝變化不靈(ling)敏(min)的(de)輸出電阻特性的(de)技術。

背景技術：

通常，影(ying)(ying)像(xiang)(xiang)顯(xian)(xian)示(shi)裝(zhuang)置可(ke)包括：影(ying)(ying)像(xiang)(xiang)信(xin)號(hao)處(chu)理(li)(li)主(zhu)機(ji)，接收來自(zi)(zi)天空電(dian)波、線纜(lan)以(yi)及其他外部裝(zhuang)置(VCR、DVD等)的(de)影(ying)(ying)像(xiang)(xiang)信(xin)號(hao)(Audio/Video signal)，對(dui)其進行影(ying)(ying)像(xiang)(xiang)處(chu)理(li)(li)并輸出；顯(xian)(xian)示(shi)面板(ban)(ban)(Display pannel)，將(jiang)由影(ying)(ying)像(xiang)(xiang)信(xin)號(hao)處(chu)理(li)(li)主(zhu)機(ji)處(chu)理(li)(li)的(de)影(ying)(ying)像(xiang)(xiang)顯(xian)(xian)示(shi)在畫面中。此時，顯(xian)(xian)示(shi)面板(ban)(ban)和影(ying)(ying)像(xiang)(xiang)信(xin)號(hao)處(chu)理(li)(li)主(zhu)機(ji)可(ke)以(yi)形(xing)成(cheng)為(wei)(wei)一體型，也可(ke)以(yi)構成(cheng)為(wei)(wei)各自(zi)(zi)分離。

此(ci)外，顯(xian)示(shi)面板和影像信號(hao)處理主(zhu)機(ji)通(tong)常利用低(di)(di)電壓差分(fen)信號(hao)(Low Voltage Differential Signal：LVDS)接(jie)口(kou)來(lai)傳(chuan)(chuan)輸影像信號(hao)。LVDS接(jie)口(kou)為將數(shu)字信息通(tong)過銅線以(yi)高(gao)速傳(chuan)(chuan)輸到平板顯(xian)示(shi)器的傳(chuan)(chuan)輸方法。此(ci)時，低(di)(di)電壓(LV，low voltage)為LVDS使用比(bi)標準電壓低(di)(di)的電壓的意思。

最近，隨著對高速數據(ju)生成(cheng)及處理的(de)(de)要求的(de)(de)增(zeng)大，將(jiang)數據(ju)從一個(ge)地點(dian)傳輸到另一個(ge)地點(dian)的(de)(de)能(neng)力(li)成(cheng)為判斷整個(ge)系統性能(neng)的(de)(de)尺度。作為用(yong)于這樣(yang)的(de)(de)高速數據(ju)傳輸的(de)(de)解決方案，LVDS接(jie)口引人矚目。

這樣的(de)(de)LVDS接口(kou)在主板(ban)和面板(ban)之(zhi)間(jian)使(shi)用更少的(de)(de)電(dian)線(xian)，因此在筆記本電(dian)腦中得到廣泛使(shi)用。此外，實際情(qing)況(kuang)為該技術在多數的(de)(de)自立型平板(ban)顯示(shi)器的(de)(de)圖像定標器(scaler)和面板(ban)之(zhi)間(jian)也(ye)得到廣泛使(shi)用。

LVDS接口方(fang)式為(wei)，與現(xian)有的(de)(de)利用(yong)單(dan)端信(xin)(xin)號(hao)(Single-Ended Signal)的(de)(de)方(fang)法強相(xiang)比(bi)，抗噪聲(sheng)能力(li)強，與利用(yong)偽射(she)極耦合邏輯(ji)(pECL，pseudo-Emitter Coupled Logic)的(de)(de)方(fang)法相(xiang)比(bi)，信(xin)(xin)號(hao)終端處理(Signal Termination)簡(jian)單(dan)，可進行Gbps以上的(de)(de)超高速傳(chuan)輸和接收的(de)(de)串行通信(xin)(xin)(Serial Communication)方(fang)法。

此外(wai)，LVDS接口利用(yong)低電壓，因此具有減(jian)少(shao)電磁(ci)干擾(Electro Magnetic Interference：EMI)、減(jian)少(shao)耗電的優(you)點(dian)。因這些(xie)優(you)點(dian)，LVDS接口不僅適用(yong)于(yu)芯片(Chip)間的數(shu)據傳(chuan)輸，還適用(yong)于(yu)板(Board)間的數(shu)據傳(chuan)輸等各種領域(yu)。

技術實現要素：

(技術問題)

本發明是為了(le)解決前(qian)述的現有(you)問題而提(ti)出的，目的在于(yu)使低電(dian)壓差分信號(hao)傳(chuan)送器具有(you)對工(gong)藝變化不靈敏(min)的輸出電(dian)阻特(te)性。

(解決問題的手段)

根據本發(fa)明的(de)實(shi)施例的(de)低電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)差(cha)分信號(hao)(hao)傳送(song)器(Low voltage differential signal transmitter)的(de)特征在(zai)于，包(bao)(bao)括(kuo)(kuo)：輸(shu)入(ru)驅(qu)動(dong)(dong)部，包(bao)(bao)括(kuo)(kuo)多(duo)個(ge)前置(zhi)驅(qu)動(dong)(dong)器，驅(qu)動(dong)(dong)正輸(shu)入(ru)信號(hao)(hao)和負輸(shu)入(ru)信號(hao)(hao)來(lai)(lai)輸(shu)出具有上拉電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)電(dian)(dian)(dian)(dian)(dian)(dian)平(ping)的(de)多(duo)個(ge)驅(qu)動(dong)(dong)信號(hao)(hao)和具有下拉電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)電(dian)(dian)(dian)(dian)(dian)(dian)平(ping)的(de)多(duo)個(ge)驅(qu)動(dong)(dong)信號(hao)(hao)；電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)發(fa)生器，調節電(dian)(dian)(dian)(dian)(dian)(dian)源電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)來(lai)(lai)生成第(di)一驅(qu)動(dong)(dong)電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)；以及主驅(qu)動(dong)(dong)部，包(bao)(bao)括(kuo)(kuo)借助于多(duo)個(ge)驅(qu)動(dong)(dong)信號(hao)(hao)而(er)選(xuan)擇性地導(dao)通(tong)的(de)多(duo)個(ge)開(kai)關元(yuan)件(jian)，向差(cha)分輸(shu)出端選(xuan)擇性地提供第(di)一驅(qu)動(dong)(dong)電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)，利用上拉電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)電(dian)(dian)(dian)(dian)(dian)(dian)平(ping)和下拉電(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)電(dian)(dian)(dian)(dian)(dian)(dian)平(ping)來(lai)(lai)調節多(duo)個(ge)開(kai)關元(yuan)件(jian)的(de)導(dao)通(tong)電(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)。

(發明的效果)

本發(fa)明(ming)提供如下效果：與傳輸(shu)(shu)線路(lu)的(de)(de)特性阻(zu)抗的(de)(de)匹配(Matching)特性不受半導(dao)體(ti)生(sheng)產(chan)工藝(yi)的(de)(de)偏差的(de)(de)影響(xiang)，防止(zhi)信(xin)號(hao)(hao)的(de)(de)傳輸(shu)(shu)速(su)度為高速(su)時可能發(fa)生(sheng)的(de)(de)信(xin)號(hao)(hao)的(de)(de)反射，而可傳輸(shu)(shu)不失(shi)真的(de)(de)信(xin)號(hao)(hao)。

此(ci)外，本(ben)發(fa)明的(de)優選(xuan)實(shi)施例僅(jin)是(shi)例示的(de)目的(de)，本(ben)發(fa)明所屬技術領域的(de)普通技術人員(yuan)可通過權利(li)要(yao)求(qiu)范(fan)圍(wei)的(de)技術思(si)想和范(fan)圍(wei)進行多種修正(zheng)、變更、代替及(ji)附加，這些修正(zheng)、變更等應(ying)視為屬于本(ben)發(fa)明權利(li)要(yao)求(qiu)范(fan)圍(wei)。

附圖說明

圖1為根據本發明實施例的(de)關于低電(dian)壓差分信號傳送器(qi)的(de)概念圖。

圖(tu)2為關(guan)于圖(tu)1的發送器(qi)的詳(xiang)細(xi)電(dian)路圖(tu)。

圖(tu)3為(wei)關于(yu)圖(tu)2的上拉控制部的詳細結構圖(tu)。

圖4為關于圖2的下拉控(kong)制部的詳細結(jie)構(gou)圖。

圖5為關于圖1的(de)發送器的(de)另一實(shi)施例(li)。

圖(tu)(tu)6為關(guan)于圖(tu)(tu)5的上拉(la)控制部(bu)的詳細結構圖(tu)(tu)。

圖7為關于圖5的下(xia)拉控制部的詳細結(jie)構圖。

圖(tu)8為關于圖(tu)1的發送(song)器的工作時序圖(tu)。

具體實施方式

以(yi)下(xia)，參照(zhao)附圖對本(ben)發明的實施例(li)進行詳細說明。

圖(tu)1為根據本發(fa)明(ming)實施例的關于低電壓差分(fen)信號傳(chuan)送器的概念圖(tu)。

低電(dian)壓差(cha)分信(xin)號傳(chuan)送器為可以(yi)高速工作并具(ju)有低電(dian)流(liu)消耗及低電(dian)磁干(gan)擾(EMI:Electromagnetic Interference)的特性(xing)的電(dian)路，在(zai)圖像傳(chuan)感(gan)器、液晶顯示裝置驅動(dong)芯片(LDI:LCD Driver IC)及通信(xin)等需要(yao)高速數據(ju)傳(chuan)輸的領域中得(de)到使用。

低電壓(ya)差分(fen)信(xin)號傳送器包括發送器100、傳輸線路200、接收器300、終端電阻400、500。

發(fa)(fa)送(song)器(qi)100經(jing)由輸(shu)(shu)(shu)入(ru)端(duan)子(zi)接收數(shu)(shu)據。向發(fa)(fa)送(song)器(qi)100輸(shu)(shu)(shu)入(ru)的(de)數(shu)(shu)據經(jing)由傳(chuan)輸(shu)(shu)(shu)線(xian)路(lu)200以差分(fen)(Differential)方式(shi)向接收器(qi)300側(ce)傳(chuan)輸(shu)(shu)(shu)。基于發(fa)(fa)送(song)器(qi)100輸(shu)(shu)(shu)入(ru)的(de)數(shu)(shu)據，兩個傳(chuan)輸(shu)(shu)(shu)路(lu)之間生成電位差，以此生成差分(fen)信號(hao)。另外，接收器(qi)300將經(jing)由傳(chuan)輸(shu)(shu)(shu)線(xian)路(lu)200接收的(de)差分(fen)信號(hao)轉換為CMOS電平并經(jing)由輸(shu)(shu)(shu)出(chu)端(duan)子(zi)輸(shu)(shu)(shu)出(chu)。

發送(song)器100和接收器300經由傳輸線(xian)路200相連接。各(ge)個傳輸線(xian)路200的電特(te)性相同，形成(cheng)平衡傳輸路徑，經由兩個傳輸路徑傳輸一(yi)個信(xin)號。

另外(wai)，為(wei)了(le)去除信號傳輸(shu)過程(cheng)中的(de)反射，形成(cheng)為(wei)使得傳輸(shu)線路200的(de)阻(zu)抗匹(pi)配。為(wei)此，在接收器(qi)300的(de)輸(shu)入端(duan)(duan)連接終(zhong)端(duan)(duan)(Termination)電(dian)阻(zu)400。此外(wai)，在發送器(qi)100的(de)輸(shu)出端(duan)(duan)側可追(zhui)加(jia)連接用于阻(zu)抗匹(pi)配的(de)終(zhong)端(duan)(duan)(Termination)電(dian)阻(zu)500。

圖(tu)2為關于圖(tu)1的發送器100的詳細電路圖(tu)。

發(fa)送器100包括輸入(ru)驅動部(bu)110、電壓發(fa)生器120、主驅動部(bu)130及差(cha)分輸出端DN、DP。

在此，輸入驅(qu)動(dong)(dong)部(bu)(bu)110包括(kuo)多個(ge)前(qian)(qian)置驅(qu)動(dong)(dong)器(qi)D1～D4。前(qian)(qian)置驅(qu)動(dong)(dong)器(qi)D1、D3為(wei)用于驅(qu)動(dong)(dong)主驅(qu)動(dong)(dong)部(bu)(bu)130的上拉部(bu)(bu)分(fen)的驅(qu)動(dong)(dong)部(bu)(bu)，前(qian)(qian)置驅(qu)動(dong)(dong)器(qi)D2、D4為(wei)用于驅(qu)動(dong)(dong)主驅(qu)動(dong)(dong)部(bu)(bu)130的下拉部(bu)(bu)分(fen)的驅(qu)動(dong)(dong)部(bu)(bu)。

前置(zhi)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)器(qi)(qi)D1利(li)用(yong)(yong)上(shang)(shang)拉電(dian)(dian)壓(ya)(ya)(ya)Vrup將(jiang)正輸(shu)(shu)入(ru)信(xin)號(hao)INP預(yu)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)而(er)生(sheng)成驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)電(dian)(dian)壓(ya)(ya)(ya)VP1。前置(zhi)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)器(qi)(qi)D2利(li)用(yong)(yong)下拉電(dian)(dian)壓(ya)(ya)(ya)Vrdn將(jiang)正輸(shu)(shu)入(ru)信(xin)號(hao)INP預(yu)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)而(er)生(sheng)成驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)電(dian)(dian)壓(ya)(ya)(ya)VP2。前置(zhi)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)器(qi)(qi)D3利(li)用(yong)(yong)上(shang)(shang)拉電(dian)(dian)壓(ya)(ya)(ya)Vrup將(jiang)負輸(shu)(shu)入(ru)信(xin)號(hao)INN預(yu)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)而(er)生(sheng)成驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)電(dian)(dian)壓(ya)(ya)(ya)VN1。前置(zhi)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)器(qi)(qi)D4利(li)用(yong)(yong)下拉電(dian)(dian)壓(ya)(ya)(ya)Vrdn將(jiang)負輸(shu)(shu)入(ru)信(xin)號(hao)INN預(yu)驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)而(er)生(sheng)成驅(qu)(qu)(qu)(qu)(qu)動(dong)(dong)(dong)(dong)電(dian)(dian)壓(ya)(ya)(ya)VN2。

即，前置驅(qu)動器(qi)D1、D3利用(yong)上(shang)拉電(dian)壓Vrup來驅(qu)動，前置驅(qu)動器(qi)D2、D4利用(yong)下拉電(dian)壓Vrdn來驅(qu)動。

電壓(ya)發(fa)(fa)生器120調節電源電壓(ya)VDD來生成(cheng)主驅動(dong)部(bu)130的驅動(dong)電壓(ya)Vreg。電壓(ya)發(fa)(fa)生器120將所生成(cheng)的驅動(dong)電壓(ya)Vreg供給至(zhi)主驅動(dong)部(bu)130的開關元件(jian)M1、M2。

主驅動部130包括多個(ge)開關(guan)(guan)元(yuan)件M1～M4。開關(guan)(guan)元(yuan)件M1～M4可以(yi)由場(chang)效應晶體管(FET，field effect transistor)構成(cheng)。

在(zai)(zai)此(ci)，開(kai)(kai)關(guan)(guan)(guan)元(yuan)件(jian)(jian)M1、M3串聯(lian)連接(jie)(jie)在(zai)(zai)驅(qu)(qu)動(dong)(dong)電(dian)(dian)壓(ya)Vreg的施(shi)加端(duan)(duan)(duan)和接(jie)(jie)地(Ground)GND電(dian)(dian)壓(ya)端(duan)(duan)(duan)之(zhi)間(jian)。驅(qu)(qu)動(dong)(dong)電(dian)(dian)壓(ya)VP1經由柵極端(duan)(duan)(duan)子(zi)(zi)施(shi)加于開(kai)(kai)關(guan)(guan)(guan)元(yuan)件(jian)(jian)M1，驅(qu)(qu)動(dong)(dong)電(dian)(dian)壓(ya)VN2經由柵極端(duan)(duan)(duan)子(zi)(zi)施(shi)加于開(kai)(kai)關(guan)(guan)(guan)元(yuan)件(jian)(jian)M3。另(ling)外，開(kai)(kai)關(guan)(guan)(guan)元(yuan)件(jian)(jian)M2、M4串聯(lian)連接(jie)(jie)在(zai)(zai)驅(qu)(qu)動(dong)(dong)電(dian)(dian)壓(ya)Vreg的施(shi)加端(duan)(duan)(duan)和接(jie)(jie)地GND電(dian)(dian)壓(ya)端(duan)(duan)(duan)之(zhi)間(jian)。驅(qu)(qu)動(dong)(dong)電(dian)(dian)壓(ya)VN1經由柵極端(duan)(duan)(duan)子(zi)(zi)施(shi)加于開(kai)(kai)關(guan)(guan)(guan)元(yuan)件(jian)(jian)M2，驅(qu)(qu)動(dong)(dong)電(dian)(dian)壓(ya)VP2經由柵極端(duan)(duan)(duan)子(zi)(zi)施(shi)加于開(kai)(kai)關(guan)(guan)(guan)元(yuan)件(jian)(jian)M4。

圖2的實施(shi)例(li)中(zhong)，前置(zhi)驅動(dong)器(qi)D1～D4的數量(liang)(liang)(liang)與設置(zhi)在主驅動(dong)部130的開關元(yuan)件(jian)M1～M4的數量(liang)(liang)(liang)相對應。即，前置(zhi)驅動(dong)器(qi)D1～D4對開關元(yuan)件(jian)M1～M4進行單獨的驅動(dong)控制。在開關元(yuan)件(jian)M1～M4的數量(liang)(liang)(liang)變(bian)更的情況下，前置(zhi)驅動(dong)器(qi)D1～D4的數量(liang)(liang)(liang)也(ye)可與此對應地(di)變(bian)更。

另外(wai)，開關元(yuan)件(jian)M1、M3的(de)共同連接節點與(yu)差分(fen)輸(shu)出(chu)端(duan)DP相連接，開關元(yuan)件(jian)M2、M4的(de)共同連接節點與(yu)差分(fen)輸(shu)出(chu)端(duan)DN相連接。差分(fen)輸(shu)出(chu)端(duan)DN、DP與(yu)傳輸(shu)線路200相連接。

開(kai)關(guan)(guan)元(yuan)件M1～M4的導通(turn on)電(dian)阻成為發送器100的輸出電(dian)阻。另外(wai)，開(kai)關(guan)(guan)元(yuan)件M1～M4的導通電(dian)阻由上拉(la)電(dian)壓Vrup、下拉(la)電(dian)壓Vrdn來確(que)定(ding)。

具有此(ci)結構的(de)發送器100對(dui)前置驅動(dong)器D1～D4的(de)輸出(chu)(chu)電(dian)壓(ya)VP1、VP2、VN1、VN2單獨地調節，上述(shu)前置驅動(dong)器D1～D4的(de)輸出(chu)(chu)電(dian)壓(ya)VP1、VP2、VN1、VN2用于驅動(dong)設置于主驅動(dong)部130的(de)開關(guan)元(yuan)件M1～M4。由(you)此(ci)，使主驅動(dong)部130的(de)開關(guan)元(yuan)件M1～M4的(de)導通電(dian)阻維持一(yi)定。

例如，當驅動電(dian)壓(ya)VP1為(wei)上拉電(dian)壓(ya)Vrup且(qie)驅動電(dian)壓(ya)VP2為(wei)下拉電(dian)壓(ya)Vrdn電(dian)平時，開(kai)(kai)關(guan)(guan)元件M1、M4會導通。那(nei)么(me)，從(cong)電(dian)壓(ya)發(fa)生(sheng)器120輸(shu)(shu)(shu)(shu)(shu)出(chu)的(de)驅動電(dian)壓(ya)Vreg經(jing)由(you)開(kai)(kai)關(guan)(guan)元件M1輸(shu)(shu)(shu)(shu)(shu)出(chu)到差(cha)分(fen)輸(shu)(shu)(shu)(shu)(shu)出(chu)端(duan)(duan)(duan)DP。另外(wai)，差(cha)分(fen)輸(shu)(shu)(shu)(shu)(shu)出(chu)端(duan)(duan)(duan)DP的(de)輸(shu)(shu)(shu)(shu)(shu)出(chu)信號經(jing)由(you)傳(chuan)輸(shu)(shu)(shu)(shu)(shu)線(xian)路200并(bing)經(jing)終(zhong)端(duan)(duan)(duan)(Termination)電(dian)阻(zu)400輸(shu)(shu)(shu)(shu)(shu)入到差(cha)分(fen)輸(shu)(shu)(shu)(shu)(shu)出(chu)端(duan)(duan)(duan)DN，經(jing)由(you)開(kai)(kai)關(guan)(guan)元件M4輸(shu)(shu)(shu)(shu)(shu)出(chu)到接地電(dian)壓(ya)GND端(duan)(duan)(duan)。

此時，從驅動電(dian)(dian)(dian)(dian)(dian)(dian)壓Vreg流向接地電(dian)(dian)(dian)(dian)(dian)(dian)壓GND端的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)流為(Vreg－GND)/((M1導(dao)通(tong)電(dian)(dian)(dian)(dian)(dian)(dian)阻)+(終端電(dian)(dian)(dian)(dian)(dian)(dian)阻)+(M4導(dao)通(tong)電(dian)(dian)(dian)(dian)(dian)(dian)阻))。當設該電(dian)(dian)(dian)(dian)(dian)(dian)流為Iref時，差分輸(shu)(shu)出端DP上的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)壓為Vreg－Iref×(M1導(dao)通(tong)電(dian)(dian)(dian)(dian)(dian)(dian)阻)，差分輸(shu)(shu)出端DN上的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)壓為GND+Iref×(M4導(dao)通(tong)電(dian)(dian)(dian)(dian)(dian)(dian)阻)。

在此，驅動(dong)電壓(ya)VN1、VN2具有(you)與驅動(dong)電壓(ya)VP1、VP2相反(fan)的極性(xing)，驅動(dong)電壓(ya)VP1、VP2為(wei)高(gao)(high)狀(zhuang)態時，驅動(dong)電壓(ya)VN1、VN2為(wei)低(low)狀(zhuang)態，使開關元件(jian)M2、M3關斷(turn off)。

相(xiang)反，驅動(dong)電壓VN1、VN2為高(gao)狀(zhuang)態時，開關(guan)元(yuan)件M2、M3導通。由(you)此，驅動(dong)電壓Vreg經(jing)由(you)開關(guan)元(yuan)件M2輸(shu)(shu)(shu)(shu)(shu)出(chu)到差(cha)分(fen)輸(shu)(shu)(shu)(shu)(shu)出(chu)端DN。另外(wai)，差(cha)分(fen)輸(shu)(shu)(shu)(shu)(shu)出(chu)端DN的(de)輸(shu)(shu)(shu)(shu)(shu)出(chu)信號經(jing)由(you)傳輸(shu)(shu)(shu)(shu)(shu)線路200并經(jing)終端電阻400輸(shu)(shu)(shu)(shu)(shu)入到差(cha)分(fen)輸(shu)(shu)(shu)(shu)(shu)出(chu)端DP，經(jing)由(you)開關(guan)元(yuan)件M3輸(shu)(shu)(shu)(shu)(shu)出(chu)到接(jie)地(di)電壓GND端。

此時，從驅動電(dian)(dian)壓(ya)Vreg流(liu)(liu)(liu)向接(jie)地電(dian)(dian)壓(ya)GND的(de)電(dian)(dian)流(liu)(liu)(liu)為(Vreg－GND)/((M2導通電(dian)(dian)阻(zu))+(終端電(dian)(dian)阻(zu))+(M3導通電(dian)(dian)阻(zu)))。當設該電(dian)(dian)流(liu)(liu)(liu)為Iref時，差(cha)分輸出端DN上(shang)的(de)電(dian)(dian)壓(ya)為Vreg－Iref×(M2導通電(dian)(dian)阻(zu))，差(cha)分輸出端DP上(shang)的(de)電(dian)(dian)壓(ya)為GND+Iref×(M3導通電(dian)(dian)阻(zu))。

在此，當驅動電(dian)壓VN1、VN2為高狀(zhuang)態時，驅動電(dian)壓VP1、VP2為低狀(zhuang)態，開(kai)關元件M1、M4關斷(duan)。

圖(tu)3為關于圖(tu)2的上拉控制部111的詳細(xi)結(jie)構圖(tu)。

上拉(la)控制部(bu)(bu)111生成供給至前(qian)置驅動器(qi)(qi)D1、D3的上拉(la)電壓Vrup。這種(zhong)上拉(la)控制部(bu)(bu)111包括高(gao)電壓發(fa)生器(qi)(qi)112、電壓發(fa)生器(qi)(qi)113、放大器(qi)(qi)114、恒定電流源(yuan)115、開(kai)關元件M5及上拉(la)電壓生成部(bu)(bu)PU。

在此，高電(dian)(dian)壓(ya)(ya)發生(sheng)器112相應(ying)于(yu)電(dian)(dian)源(yuan)電(dian)(dian)壓(ya)(ya)VDD而(er)生(sheng)成高電(dian)(dian)壓(ya)(ya)Vhigh并供給至放大器114。電(dian)(dian)壓(ya)(ya)發生(sheng)器113調(diao)節(jie)電(dian)(dian)源(yuan)電(dian)(dian)壓(ya)(ya)VDD來生(sheng)成驅動(dong)(dong)電(dian)(dian)壓(ya)(ya)Vreg2并供給至開(kai)關(guan)元件M5。在此，驅動(dong)(dong)電(dian)(dian)壓(ya)(ya)Vreg2可以具有與驅動(dong)(dong)電(dian)(dian)壓(ya)(ya)Vreg相同的電(dian)(dian)壓(ya)(ya)電(dian)(dian)平。

放(fang)大器(qi)(qi)114相應于電(dian)源(yuan)電(dian)壓(ya)VDD而將高(gao)電(dian)壓(ya)Vhigh和反(fan)饋(kui)電(dian)壓(ya)Vfeedh進行比較及(ji)放(fang)大，輸出上拉驅動信號VPU。即，放(fang)大器(qi)(qi)114經由(you)同相(正)輸入(ru)端(duan)接收高(gao)電(dian)壓(ya)Vhigh，經由(you)反(fan)相(負)輸入(ru)端(duan)接收反(fan)饋(kui)電(dian)壓(ya)Vfeedh。

此外(wai)，恒定電(dian)(dian)流源(yuan)115連接在開關(guan)元(yuan)件M5和接地(di)GND電(dian)(dian)壓(ya)端之間，使與(yu)反饋電(dian)(dian)壓(ya)Vfeedh對應的恒定電(dian)(dian)流Iref流動。另外(wai)，上(shang)拉(la)電(dian)(dian)壓(ya)生成部PU相應于電(dian)(dian)源(yuan)電(dian)(dian)壓(ya)VDD而(er)調節(jie)上(shang)拉(la)驅動信號VPU來生成上(shang)拉(la)電(dian)(dian)壓(ya)Vrup，并(bing)供(gong)給至前置驅動器D1、D3。

另(ling)外，開關元(yuan)件M5連接在驅(qu)動電(dian)(dian)壓(ya)Vreg2施加端和(he)(he)恒定電(dian)(dian)流源115之間，上(shang)拉驅(qu)動信號VPU經由柵極端子而施加。開關元(yuan)件M5為具有與圖(tu)(tu)2的(de)開關元(yuan)件M1、M2相(xiang)(xiang)同的(de)大(da)小(xiao)和(he)(he)相(xiang)(xiang)同的(de)布圖(tu)(tu)(Layout)的(de)復制品(Replica)。在此，假設(she)開關元(yuan)件M1、M2具有相(xiang)(xiang)同的(de)大(da)小(xiao)和(he)(he)相(xiang)(xiang)同的(de)布圖(tu)(tu)。

在放大器(qi)114的增(zeng)益(DC gain)足夠大的情況下(例(li)如(ru)60dB以上)，調節上拉(la)驅(qu)動(dong)信號VPU的電平，使得反饋(kui)電壓(ya)Vfeedh與高電壓(ya)Vhigh的值相同。此時，開(kai)關元件M5的導通(trun on)電阻為(Vreg2－Vhigh)/Iref。

上(shang)(shang)拉電壓(ya)生(sheng)(sheng)(sheng)(sheng)成(cheng)部PU對(dui)如此地調(diao)(diao)節了的上(shang)(shang)拉驅動信號VPU進行調(diao)(diao)節而(er)生(sheng)(sheng)(sheng)(sheng)成(cheng)上(shang)(shang)拉電壓(ya)Vrup。上(shang)(shang)拉電壓(ya)生(sheng)(sheng)(sheng)(sheng)成(cheng)部PU提供(gong)所生(sheng)(sheng)(sheng)(sheng)成(cheng)的上(shang)(shang)拉電壓(ya)Vrup作為前置驅動器(qi)D1、D3的電源(yuan)。

接收上拉(la)電(dian)(dian)壓(ya)Vrup作(zuo)為電(dian)(dian)源電(dian)(dian)壓(ya)的(de)(de)前置驅(qu)動(dong)器D1、D3根據驅(qu)動(dong)電(dian)(dian)壓(ya)VP1、VN1來控制開(kai)關(guan)元件M1、M2的(de)(de)驅(qu)動(dong)。即，驅(qu)動(dong)電(dian)(dian)壓(ya)VP1、VN1的(de)(de)高狀態電(dian)(dian)壓(ya)成為上拉(la)電(dian)(dian)壓(ya)Vrup電(dian)(dian)平。

主驅動部(bu)130的(de)(de)(de)開(kai)關(guan)元件(jian)(jian)M1、M2的(de)(de)(de)施加了(le)上拉電(dian)壓(ya)Vrup時的(de)(de)(de)導通電(dian)阻值與開(kai)關(guan)元件(jian)(jian)M5的(de)(de)(de)導通電(dian)阻值相同，即為(Vreg2－Vhigh)/Iref。此時，驅動電(dian)壓(ya)Vreg2優選地具(ju)有比高電(dian)壓(ya)Vhigh更高的(de)(de)(de)電(dian)壓(ya)電(dian)平。

本(ben)發明(ming)的(de)實施例(li)中，與開(kai)關(guan)(guan)元(yuan)件M1、M2的(de)工藝變化(hua)相(xiang)對應地，借助于以作為復制(zhi)品(pin)的(de)開(kai)關(guan)(guan)元(yuan)件M5和放大器114、帶隙電壓為基礎而生成的(de)高電壓Vhigh及恒定(ding)電流源115，來調節上拉電壓Vrup的(de)電平，使(shi)得開(kai)關(guan)(guan)元(yuan)件M1、M2的(de)輸出(chu)電阻(zu)一定(ding)，因(yin)此開(kai)關(guan)(guan)元(yuan)件M1、M2的(de)導通電阻(zu)值不受工藝變化(hua)的(de)影響。

圖(tu)4為(wei)關于圖(tu)2的下拉控(kong)制部116的詳(xiang)細結(jie)構(gou)圖(tu)。

下拉(la)控制部116生成供給至(zhi)前置驅動器(qi)(qi)D2、D4的(de)下拉(la)電(dian)壓Vrdn。這(zhe)樣的(de)下拉(la)控制部116包括低(di)電(dian)壓發生器(qi)(qi)117、放大器(qi)(qi)118、恒(heng)定電(dian)流源119、開(kai)關元件M6及下拉(la)電(dian)壓生成部PD。

在此，低電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)發生器(qi)117相應于(yu)電(dian)源電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)VDD而生成低電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)Vlow，并供給至(zhi)放大(da)(da)(da)器(qi)118。放大(da)(da)(da)器(qi)118相應于(yu)電(dian)源電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)VDD而將低電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)Vlow和(he)反饋電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)Vfeedl進(jin)行比較(jiao)及放大(da)(da)(da)，輸(shu)(shu)出下拉驅動信號VPD。即，放大(da)(da)(da)器(qi)118經由(you)反相輸(shu)(shu)入端接收(shou)低電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)Vlow，經由(you)同相輸(shu)(shu)入端接收(shou)反饋電(dian)壓(ya)(ya)(ya)(ya)(ya)(ya)Vfeedl。

此(ci)外，恒定電(dian)流(liu)源119連接在電(dian)源電(dian)壓VDD施加端和開關元件M6之間，使與反饋電(dian)壓Vfeedl相對應的恒定電(dian)流(liu)Iref流(liu)動。此(ci)外，下(xia)拉電(dian)壓生成(cheng)部PD應電(dian)源電(dian)壓VDD而調節下(xia)拉驅動信號VPD來(lai)生成(cheng)下(xia)拉電(dian)壓Vrdn，并(bing)供給(gei)至前置驅動器D2、D4。

另外，開(kai)關(guan)元(yuan)(yuan)件M6連接在(zai)恒定電流源119和(he)接地GND電壓端之間，下拉驅動信號VPD經由柵極端子(zi)而(er)施加。開(kai)關(guan)元(yuan)(yuan)件M6為具有與圖(tu)2的(de)開(kai)關(guan)元(yuan)(yuan)件M3、M4相(xiang)同(tong)(tong)的(de)大小(xiao)和(he)同(tong)(tong)樣的(de)布圖(tu)(Layout)的(de)復制(zhi)品(pin)(Replica)。在(zai)此，假設開(kai)關(guan)元(yuan)(yuan)件M3、M4具有相(xiang)同(tong)(tong)的(de)大小(xiao)和(he)相(xiang)同(tong)(tong)的(de)布圖(tu)。

在(zai)放大器118的(de)增益(DC gain)足夠(gou)大的(de)情況下(xia)(例如60dB以上)，調節下(xia)拉(la)驅動信號VPD的(de)電(dian)平，使得(de)反饋電(dian)壓Vfeedl與低電(dian)壓Vlow的(de)值(zhi)相同。此時，開關元(yuan)件M6的(de)導通(turn on)電(dian)阻為Vlow/Iref。

下拉電(dian)(dian)壓(ya)(ya)生成部PD對以如上(shang)所述的(de)(de)方式(shi)調節了的(de)(de)下拉驅動信號VPD進行調節而生成下拉電(dian)(dian)壓(ya)(ya)Vrdn。下拉電(dian)(dian)壓(ya)(ya)生成部PD提(ti)供所生成的(de)(de)下拉電(dian)(dian)壓(ya)(ya)Vrdn作(zuo)為前置驅動器D2、D4的(de)(de)電(dian)(dian)源。

接收(shou)下(xia)拉電(dian)(dian)壓(ya)Vrdn作為(wei)電(dian)(dian)源電(dian)(dian)壓(ya)的(de)前(qian)置驅(qu)(qu)動(dong)器D2、D4根據(ju)驅(qu)(qu)動(dong)電(dian)(dian)壓(ya)VP2、VN2來(lai)控(kong)制(zhi)開關元件M3、M4的(de)驅(qu)(qu)動(dong)。即，驅(qu)(qu)動(dong)電(dian)(dian)壓(ya)VP2、VN2的(de)高(gao)狀態電(dian)(dian)壓(ya)成為(wei)下(xia)拉電(dian)(dian)壓(ya)Vrdn電(dian)(dian)平(ping)。

向主驅動(dong)部130的(de)(de)開關元(yuan)件(jian)(jian)M3、M4施加下拉電(dian)(dian)(dian)(dian)壓(ya)Vrdn時的(de)(de)導通電(dian)(dian)(dian)(dian)阻值與開關元(yuan)件(jian)(jian)M6的(de)(de)導通電(dian)(dian)(dian)(dian)阻值相同，即為Vlow/Iref。本(ben)發(fa)明的(de)(de)實(shi)施例中(zhong)，與開關元(yuan)件(jian)(jian)M3、M4的(de)(de)工(gong)藝(yi)變(bian)化相對應地，借助于以作(zuo)為復制品的(de)(de)開關元(yuan)件(jian)(jian)M6和放大器118及(ji)帶(dai)隙電(dian)(dian)(dian)(dian)壓(ya)為基礎而生成的(de)(de)低電(dian)(dian)(dian)(dian)壓(ya)Vlow及(ji)恒定電(dian)(dian)(dian)(dian)流源119，來調節下拉電(dian)(dian)(dian)(dian)壓(ya)Vrdn的(de)(de)電(dian)(dian)(dian)(dian)平，使得(de)開關元(yuan)件(jian)(jian)M3、M4的(de)(de)輸(shu)出(chu)電(dian)(dian)(dian)(dian)阻一(yi)定，由此開關元(yuan)件(jian)(jian)M3、M4的(de)(de)導通電(dian)(dian)(dian)(dian)阻值不(bu)受工(gong)藝(yi)變(bian)化的(de)(de)影響。

圖5為關于(yu)圖1的(de)發送器100的(de)另一(yi)實施例。

根據圖5的實(shi)施(shi)例的發(fa)送器100_1包(bao)括輸(shu)入(ru)驅(qu)動部(bu)110_1、電(dian)(dian)(dian)(dian)壓(ya)發(fa)生器120_1、主驅(qu)動部(bu)130_1及差(cha)分輸(shu)出端DN、DP。圖5的實(shi)施(shi)例具有與(yu)圖2的實(shi)施(shi)例相同的結構。但是(shi)，主驅(qu)動部(bu)130_1包(bao)括電(dian)(dian)(dian)(dian)阻R1～R4用于防止(zhi)靜電(dian)(dian)(dian)(dian)放電(dian)(dian)(dian)(dian)(ESD，Electro Static Discharge)，這與(yu)圖2不同。

電(dian)阻(zu)R1連接(jie)(jie)在開關元(yuan)件M1和(he)(he)差(cha)分(fen)(fen)輸(shu)出端(duan)(duan)DP之(zhi)間(jian)(jian)。此(ci)外(wai)(wai)，電(dian)阻(zu)R2連接(jie)(jie)在開關元(yuan)件M2和(he)(he)差(cha)分(fen)(fen)輸(shu)出端(duan)(duan)DN之(zhi)間(jian)(jian)。此(ci)外(wai)(wai)，電(dian)阻(zu)R3連接(jie)(jie)在開關元(yuan)件M3和(he)(he)差(cha)分(fen)(fen)輸(shu)出端(duan)(duan)DP之(zhi)間(jian)(jian)。另(ling)外(wai)(wai)，電(dian)阻(zu)R4連接(jie)(jie)在開關元(yuan)件M4和(he)(he)差(cha)分(fen)(fen)輸(shu)出端(duan)(duan)DN之(zhi)間(jian)(jian)。即(ji)，電(dian)阻(zu)R2、R4連接(jie)(jie)在差(cha)分(fen)(fen)輸(shu)出端(duan)(duan)DN和(he)(he)開關元(yuan)件M2、M4之(zhi)間(jian)(jian)，電(dian)阻(zu)R1、R3連接(jie)(jie)在差(cha)分(fen)(fen)輸(shu)出端(duan)(duan)DP和(he)(he)開關元(yuan)件M1、M3之(zhi)間(jian)(jian)。

差分輸出端DP、DN作為連(lian)(lian)接半導體芯片內部(bu)和外部(bu)的連(lian)(lian)接點(Interface，接口)，在(zai)差分輸出端DP、DN可能出現靜電放(fang)電(ESD，Electro Static Discharge)的問題。為應對這種情況(kuang)，在(zai)與傳輸線(xian)路(lu)200連(lian)(lian)接的差分輸出端DP、DN上連(lian)(lian)接電阻R1～R4。

開關元件M1～M4的導通電阻(zu)(zu)與電阻(zu)(zu)R1～R4的電阻(zu)(zu)值之和(he)為(wei)發送器100_1的輸出(chu)電阻(zu)(zu)。另外(wai)，開關元件M1～M4的導通電阻(zu)(zu)由上拉電壓Vrup、下拉電壓Vrdn所確定(ding)。

關(guan)于差分輸出(chu)端(duan)DP、DN和(he)恒(heng)定電(dian)(dian)(dian)(dian)(dian)流源115、119的電(dian)(dian)(dian)(dian)(dian)壓(ya)，要在各開(kai)關(guan)元件(jian)M1～M4的晶體管(guan)導通(turn on)電(dian)(dian)(dian)(dian)(dian)阻上(shang)加上(shang)主驅(qu)動部130_1的用于ESD的電(dian)(dian)(dian)(dian)(dian)阻R1～R4的電(dian)(dian)(dian)(dian)(dian)阻值R。即，通過開(kai)關(guan)元件(jian)M1和(he)電(dian)(dian)(dian)(dian)(dian)阻R1的輸出(chu)電(dian)(dian)(dian)(dian)(dian)阻的情形成(cheng)為(開(kai)關(guan)元件(jian)M1的導通電(dian)(dian)(dian)(dian)(dian)阻+電(dian)(dian)(dian)(dian)(dian)阻R1的電(dian)(dian)(dian)(dian)(dian)阻值R)。

圖6為關于圖5的上拉控制部111_1的詳(xiang)細結構圖。

圖6的(de)實(shi)施(shi)例具有(you)與圖3相同(tong)的(de)結構，但在開關元件M5和(he)恒(heng)定電(dian)流源115之間還設(she)置(zhi)電(dian)阻(zu)R5，這與圖3不同(tong)。

在放大器114的增益(DC gain)足(zu)夠大的情(qing)況下(xia)(例如60dB以上(shang))，調(diao)節上(shang)拉驅(qu)動(dong)信號(hao)VPU的電(dian)(dian)平，使得反饋(kui)電(dian)(dian)壓Vfeedh與高電(dian)(dian)壓Vhigh的值相同(tong)。此時，開(kai)關元件(jian)M5的導通(tong)(trun on)電(dian)(dian)阻(zu)與電(dian)(dian)阻(zu)R5之和為(wei)(Vreg2－Vhigh)/Iref。

上(shang)(shang)拉(la)電(dian)壓(ya)生(sheng)成(cheng)部PU對以如上(shang)(shang)所述(shu)的方式調(diao)節(jie)了的上(shang)(shang)拉(la)驅(qu)動(dong)信號VPU進行調(diao)節(jie)而生(sheng)成(cheng)上(shang)(shang)拉(la)電(dian)壓(ya)Vrup。上(shang)(shang)拉(la)電(dian)壓(ya)生(sheng)成(cheng)部PU提供所生(sheng)成(cheng)的上(shang)(shang)拉(la)電(dian)壓(ya)Vrup作為前置驅(qu)動(dong)器(qi)D1、D3的電(dian)源。

接收上拉(la)電壓(ya)Vrup作為電源(yuan)電壓(ya)的前置驅(qu)動(dong)器(qi)D1、D3根據驅(qu)動(dong)電壓(ya)VP1、VN1來控(kong)制開關元件M1、M2的驅(qu)動(dong)。即，驅(qu)動(dong)電壓(ya)VP1、VN1的高(gao)狀(zhuang)態電壓(ya)成為上拉(la)電壓(ya)Vrup電平(ping)。

主驅(qu)動部130的(de)(de)開(kai)(kai)關(guan)(guan)元件(jian)M1、M2的(de)(de)施(shi)加(jia)了(le)上拉電(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)Vrup時(shi)的(de)(de)導(dao)通電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)和(he)(he)各電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)R1、R2之和(he)(he)與(yu)開(kai)(kai)關(guan)(guan)元件(jian)M5的(de)(de)導(dao)通電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)和(he)(he)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)R5之和(he)(he)相同，即為(wei)(Vreg2－Vhigh)/Iref。此(ci)時(shi)，驅(qu)動電(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)Vreg2優(you)選地(di)具(ju)有比高(gao)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)Vhigh更高(gao)的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平(ping)。在本發明的(de)(de)實施(shi)例中(zhong)，與(yu)開(kai)(kai)關(guan)(guan)元件(jian)M1、M2及(ji)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)R1、R2的(de)(de)工(gong)藝變化相對(dui)應地(di)，借助于以作(zuo)為(wei)復制品的(de)(de)開(kai)(kai)關(guan)(guan)元件(jian)M5和(he)(he)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)R5、放大器114、帶隙電(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)為(wei)基礎而生成(cheng)的(de)(de)高(gao)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)Vhigh及(ji)恒定電(dian)(dian)(dian)(dian)(dian)(dian)(dian)流源(yuan)115，來(lai)調節上拉電(dian)(dian)(dian)(dian)(dian)(dian)(dian)壓(ya)(ya)(ya)Vrup的(de)(de)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)平(ping)，使得開(kai)(kai)關(guan)(guan)元件(jian)M1、M2的(de)(de)導(dao)通電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)及(ji)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)R1、R2之和(he)(he)一(yi)定，因此(ci)開(kai)(kai)關(guan)(guan)元件(jian)M1、M2的(de)(de)導(dao)通電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)和(he)(he)電(dian)(dian)(dian)(dian)(dian)(dian)(dian)阻(zu)(zu)(zu)R1、R2之和(he)(he)不受工(gong)藝變化的(de)(de)影響。

圖(tu)7為關(guan)于圖(tu)5的(de)下拉控制(zhi)部116_1的(de)詳細結構圖(tu)。

圖(tu)7的(de)實施例(li)具有與(yu)圖(tu)4相同的(de)結構，但在開關元件M6和恒定電(dian)流源119之間還設置(zhi)電(dian)阻R6，這與(yu)圖(tu)4不同。

在(zai)放大器118的(de)增益(DC gain)足夠大的(de)情況下(xia)(例如60dB以上)，調節下(xia)拉驅動信(xin)號(hao)VPD的(de)電平，使(shi)得反饋電壓(ya)Vfeedl與低電壓(ya)Vlow的(de)值(zhi)相同。此(ci)時，開關元(yuan)件M6的(de)導通(trun on)電阻與電阻R6之和為Vlow/Iref。

下(xia)拉電壓生(sheng)成部PD對以如(ru)上(shang)所(suo)述的(de)方式調(diao)(diao)節了的(de)下(xia)拉驅(qu)動信號VPD進行調(diao)(diao)節而(er)生(sheng)成下(xia)拉電壓Vrdn。下(xia)拉電壓生(sheng)成部PD提供所(suo)生(sheng)成的(de)下(xia)拉電壓Vrdn作為(wei)前置驅(qu)動器D2、D4的(de)電源。

接(jie)收(shou)下拉電(dian)(dian)壓(ya)Vrdn作為電(dian)(dian)源電(dian)(dian)壓(ya)的(de)前置驅動器D2、D4根據(ju)驅動電(dian)(dian)壓(ya)VP2、VN2來控制(zhi)開關元件(jian)M3、M4的(de)驅動。即(ji)，驅動電(dian)(dian)壓(ya)VP2、VN2的(de)高(gao)狀態電(dian)(dian)壓(ya)成為下拉電(dian)(dian)壓(ya)Vrdn電(dian)(dian)平。

向主驅(qu)動部130的開(kai)關(guan)元(yuan)件(jian)M3、M4施(shi)加下拉電(dian)(dian)壓(ya)(ya)Vrdn時的導通(tong)(tong)電(dian)(dian)阻(zu)(zu)(zu)(zu)和(he)(he)(he)(he)電(dian)(dian)阻(zu)(zu)(zu)(zu)R3、R4之和(he)(he)(he)(he)與(yu)開(kai)關(guan)元(yuan)件(jian)M6的導通(tong)(tong)電(dian)(dian)阻(zu)(zu)(zu)(zu)和(he)(he)(he)(he)電(dian)(dian)阻(zu)(zu)(zu)(zu)R6之和(he)(he)(he)(he)相(xiang)同(tong)，即(ji)為(wei)Vlow/Iref。本(ben)發(fa)明(ming)的實施(shi)例中，與(yu)開(kai)關(guan)元(yuan)件(jian)M3、M4及電(dian)(dian)阻(zu)(zu)(zu)(zu)R3、R4的工藝變(bian)化相(xiang)對應(ying)地，借助于以(yi)作為(wei)復制品的開(kai)關(guan)元(yuan)件(jian)M6和(he)(he)(he)(he)電(dian)(dian)阻(zu)(zu)(zu)(zu)R6、放(fang)大器118、帶(dai)隙電(dian)(dian)壓(ya)(ya)為(wei)基礎而生成(cheng)的低(di)電(dian)(dian)壓(ya)(ya)Vlow及恒(heng)定(ding)電(dian)(dian)流(liu)源119，來調(diao)節下拉電(dian)(dian)壓(ya)(ya)Vrdn的電(dian)(dian)平，使得(de)開(kai)關(guan)元(yuan)件(jian)M3、M4的導通(tong)(tong)電(dian)(dian)阻(zu)(zu)(zu)(zu)和(he)(he)(he)(he)電(dian)(dian)阻(zu)(zu)(zu)(zu)R3、R4之和(he)(he)(he)(he)一定(ding)，因此(ci)開(kai)關(guan)元(yuan)件(jian)M3、M4的導通(tong)(tong)電(dian)(dian)阻(zu)(zu)(zu)(zu)和(he)(he)(he)(he)電(dian)(dian)阻(zu)(zu)(zu)(zu)R3、R4之和(he)(he)(he)(he)不受工藝變(bian)化的影響。

圖8為關(guan)于(yu)根據(ju)本發明實施例(li)的(de)發送(song)器100的(de)工作時(shi)序圖。

正輸入信號(hao)INP和負(fu)輸入信號(hao)INN在(zai)電(dian)源電(dian)壓VDD和接地電(dian)壓GND電(dian)平之間擺(bai)動(swing)。在(zai)此，正輸入信號(hao)INP和負(fu)輸入信號(hao)INN具有相(xiang)互相(xiang)反的相(xiang)位。

驅(qu)動(dong)(dong)電(dian)(dian)(dian)壓(ya)(ya)VP1、VN1在(zai)上拉(la)電(dian)(dian)(dian)壓(ya)(ya)Vrup和接(jie)地(di)電(dian)(dian)(dian)壓(ya)(ya)GND的(de)(de)電(dian)(dian)(dian)平之(zhi)間(jian)擺動(dong)(dong)。另(ling)外，驅(qu)動(dong)(dong)電(dian)(dian)(dian)壓(ya)(ya)VP2、VN2在(zai)下拉(la)電(dian)(dian)(dian)壓(ya)(ya)Vrdn和接(jie)地(di)電(dian)(dian)(dian)壓(ya)(ya)GND之(zhi)間(jian)擺動(dong)(dong)。在(zai)此，驅(qu)動(dong)(dong)電(dian)(dian)(dian)壓(ya)(ya)VP1、VP2和驅(qu)動(dong)(dong)電(dian)(dian)(dian)壓(ya)(ya)VN1、VN2具有相互(hu)相反的(de)(de)相位(wei)。另(ling)外，可看出(chu)，作為發送器100的(de)(de)輸出(chu)的(de)(de)差分輸出(chu)端DN、DP在(zai)高電(dian)(dian)(dian)壓(ya)(ya)Vhigh和低電(dian)(dian)(dian)壓(ya)(ya)Vlow的(de)(de)電(dian)(dian)(dian)平之(zhi)間(jian)擺動(dong)(dong)。

在此(ci)，高(gao)電(dian)(dian)(dian)壓Vhigh為Vreg－Iref×(M1導(dao)(dao)通(tong)電(dian)(dian)(dian)阻(zu)(zu))或Vreg－Iref×(M2導(dao)(dao)通(tong)電(dian)(dian)(dian)阻(zu)(zu))。另外，低(di)電(dian)(dian)(dian)壓Vlow為GND+Iref×(M4導(dao)(dao)通(tong)電(dian)(dian)(dian)阻(zu)(zu))或GND+Iref×(M3導(dao)(dao)通(tong)電(dian)(dian)(dian)阻(zu)(zu))。通(tong)常，GND為0V，因此(ci)低(di)電(dian)(dian)(dian)壓Vlow為Iref×(M4導(dao)(dao)通(tong)電(dian)(dian)(dian)阻(zu)(zu))或Iref×(M3導(dao)(dao)通(tong)電(dian)(dian)(dian)阻(zu)(zu))。

例如，在液晶顯示(shi)驅(qu)動(dong)器(qi)(qi)芯(xin)片(LDI，LCD Driver IC)或手機(ji)用(yong)(yong)圖像傳(chuan)感器(qi)(qi)等中所使(shi)用(yong)(yong)的移動(dong)行業處理器(qi)(qi)接(jie)口(MIPI，Mobile Industry Processor Interface)的情況下(xia)，標準規格是驅(qu)動(dong)電(dian)(dian)(dian)壓Vreg為400mv、高電(dian)(dian)(dian)壓Vhigh為300mV、低電(dian)(dian)(dian)壓Vlow為100mV。另外，終端(Termination)電(dian)(dian)(dian)阻300使(shi)用(yong)(yong)100歐姆。

由此(ci)，為(wei)(wei)了滿足(zu)(zu)該規格(ge)，電流Iref為(wei)(wei)2mA，各(ge)晶體管(guan)M1～M4的(de)導通(turn on)電阻(zu)(zu)要達到50歐(ou)姆，此(ci)時傳輸(shu)線路200的(de)特性(xing)阻(zu)(zu)抗匹配也(ye)會得到滿足(zu)(zu)。此(ci)時，發送(song)器100的(de)輸(shu)出電阻(zu)(zu)為(wei)(wei)50歐(ou)姆。

另外，圖(tu)5的(de)實施(shi)例的(de)情況(kuang)下(xia)，各(ge)晶體(ti)管M1～M4的(de)導(dao)通(turn-on)電(dian)(dian)阻(zu)(zu)和用于(yu)ESD的(de)電(dian)(dian)阻(zu)(zu)R之(zhi)和要達到50歐姆。但是，晶體(ti)管M1～M4的(de)導(dao)通(turn-on)電(dian)(dian)阻(zu)(zu)或用于(yu)ESD的(de)電(dian)(dian)阻(zu)(zu)R對半(ban)(ban)導(dao)體(ti)生產工藝的(de)偏差的(de)依(yi)賴度大(da)，因(yin)此在半(ban)(ban)導(dao)體(ti)生產工藝發生偏差的(de)情況(kuang)下(xia)，會(hui)直接影響發送器(qi)100的(de)輸出電(dian)(dian)阻(zu)(zu)。

在MIPI的(de)情況下，輸出電(dian)阻規格最低為40歐(ou)姆、最高為62.5歐(ou)姆，但在生產工藝的(de)偏差比率遠(yuan)高于(yu)此，因(yin)此會脫離規格。不僅如此，傳(chuan)輸線路200的(de)特性阻抗匹配也不如意(yi)，因(yin)此在信號(hao)傳(chuan)輸中(zhong)會出現反射，使得信號(hao)越趨高速時所傳(chuan)輸的(de)信號(hao)的(de)失真越大。

為(wei)(wei)此，本(ben)發明的(de)(de)實施(shi)例中，與開關(guan)(guan)(guan)元(yuan)件M1～M4及用于(yu)ESD的(de)(de)電(dian)阻R1～R4的(de)(de)工藝變化相(xiang)對(dui)應地，借助于(yu)以作為(wei)(wei)它(ta)們的(de)(de)復制品的(de)(de)開關(guan)(guan)(guan)元(yuan)件M5、M6、電(dian)阻R5、R6及帶隙電(dian)壓(ya)(ya)為(wei)(wei)基礎而生成的(de)(de)高(gao)電(dian)壓(ya)(ya)Vhigh、低電(dian)壓(ya)(ya)Vlow、恒定電(dian)流源115、119及放(fang)大器114、118，來調節上拉電(dian)壓(ya)(ya)Vrup、下拉電(dian)壓(ya)(ya)Vrdn的(de)(de)電(dian)平，因此開關(guan)(guan)(guan)元(yuan)件M1～M4的(de)(de)導通電(dian)阻值或其(qi)與R～R4之(zhi)和不受工藝變化的(de)(de)影響。